MRAM OTP Cell Parallel Write Circuit Reduces Voltage

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Solution Overview

Problem

Magnetoresistive Random Access Memory (MRAM) technologies face challenges in efficiently writing data to one-time programmable (OTP) cells, requiring lower voltage and stronger select transistors due to parasitic resistance issues during OTP writes, and struggle to differentiate between blown and unblown cells for reliable data storage.

Innovation Solution

The MRAM array is configured with OTP rows where multiple columns are connected in parallel, allowing select transistors to operate in parallel during OTP writes, reducing effective select gate impedance and enabling lower voltage OTP writes, and using distinct resistance states for read modes to distinguish between blown and unblown cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional MRAM write operations are used for OTP cells, then the write operation can be performed, but high voltage requirements and parasitic resistance issues prevent efficient writing

Engineering Contradiction:

ImproveOTP write efficiencyVSAvoidwrite voltage requirement

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Multiple select transistors from different columns are merged in parallel to form a composite select transistor for OTP rows. This combination reduces the effective select gate impedance and lowers the voltage requirement for OTP write operations, enabling efficient programming of OTP cells without excessive power consumption.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The MRAM array is segmented into regular rows and OTP-specific rows. OTP rows are specially configured with multiple columns connected in parallel, while regular rows maintain traditional single-column structures. This segmentation allows OTP operations to benefit from reduced impedance without affecting the performance of regular MRAM cells.

Inventive Principle:

Principle #1Segmentation

2Productivity

If multiple columns are connected in parallel for OTP rows, then select gate impedance is reduced and write efficiency improves, but device complexity increases

Engineering Contradiction:

ImproveOTP write speedVSAvoidcolumn connection structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The parallel column connection structure in OTP rows serves multiple functions: it reduces select gate impedance for faster writes, provides redundant selection paths for improved reliability, and maintains compatibility with standard MRAM read operations. This multi-functionality justifies the increased structural complexity by delivering multiple performance benefits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If distinct resistance states are used to differentiate blown and unblown cells, then data storage reliability improves, but manufacturing precision requirements increase

Engineering Contradiction:

Improvecell state differentiationVSAvoidresistance state control

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent utilizes changes in resistance parameters to differentiate between blown and unblown OTP cells. By monitoring the resistance state after write operations, the system can reliably determine whether a cell has been successfully programmed or remains in its initial state, providing a clear binary distinction for data storage without requiring complex additional structures.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for efficient OTP writes with reduced voltage requirements and improved data storage reliability by creating a low permanent resistance state distinguishable from unblown cells, enhancing the MRAM's ability to store and read OTP data.

Implementation Method 1

A Magnetoresistive Random Access Memory (MRAM) is a memory whose memory cells store information using magnetic states

Methodology Applied

Scientific EffectMagnetoresistance: Magnetoresistance

Implementation Method 2

the tunnel dielectric layer of the MTJ of the cells are blown during an OTP mode write to provide a very low permanent resistance

Methodology Applied

Scientific EffectDielectric breakdown:

Data Source

PatentUS11049539B1Magnetoresistive random access memory (MRAM) with OTP cells

Publication Date: 2021.06.29 NXP USA INC

AI summary

A magnetoresistive random access memory (MRAM) array has a corresponding MRAM cell, including a Magnetic Tunnel Junction (MTJ), at an intersection of each row and column. A first row of the array is configured as a single one-time-programmable (OTP) row, wherein a first MRAM cell in a first column is connected to a second MRAM cell in a second column. A first MTJ of the first MRAM cell is connected to a first bit line of the first column, and a second MTJ of the second MRAM cell is not connected to a second bit line of the second column. During a write to the first MRAM cell, write circuitry is configured to connect the first and second bit lines and the corresponding source lines such that the select transistors in the first and second MRAM cells are connected in parallel to drive a write current through the first MTJ.