MRAM Junction Stack Patterning With an Etch-Resistant Dielectric
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in patterning magnetic random access memory (MRAM) structures due to the difficulty in controlling the etch process, leading to issues such as void formation and shorts between layers, particularly in magnetic tunnel junction stacks.
Innovation Solution
The use of an etch resistant layer with higher chemical bond energy, such as amorphous carbon or carbon nitride, is introduced to control the etch process, allowing precise patterning of memory structures and protecting underlying conductive structures by reducing the removal rate of the dielectric layers, thereby minimizing voids and shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a standard etch process is used for patterning MRAM structures, then the etching speed is maintained, but void formation and shorts between layers occur due to poor etch control
Solution Approach 1:
An etch resistant layer comprising amorphous carbon or carbon nitride is introduced as an intermediary between the first dielectric layer and the memory structure. This layer acts as a mediator that provides superior etch resistance and control during the patterning process, preventing void formation and shorts while maintaining reliable device performance.
Solution Approach 2:
The patent employs a composite dielectric structure consisting of a first dielectric layer (silicon rich oxide), an etch resistant layer (amorphous carbon or carbon nitride), and a second dielectric layer. This composite material approach combines the advantages of each material to achieve both etch control and device reliability.
2Length of moving object
If the first dielectric layer thickness is reduced to decrease aspect ratio, then the aspect ratio between adjacent memory structures decreases, but voids form in the dielectric layer
Solution Approach 1:
The etch resistant layer serves as a protective intermediary that enables the use of thinner first dielectric layers without causing void formation. By providing enhanced etch resistance at the critical interface, it allows reduced dielectric thickness while maintaining structural integrity and preventing voids during the etching process.
3Device complexity
If the etch resistant layer is not used, then the manufacturing process is simpler, but shorts form between conductive structures due to excessive etching
Solution Approach 1:
The etch resistant layer acts as a protective intermediary that prevents excessive etching from reaching and shorting conductive structures. Although it adds a layer to the process, it is a single, well-defined material layer that provides critical protection during patterning operations.
Solution Approach 2:
The etch resistant layer is formed in advance before the memory structure layers are deposited and before the final patterning steps. This preliminary action ensures that the protective barrier is in place before any etching operations that could cause shorts between conductive structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances etch control, reducing the aspect ratio between memory structures, minimizing voids, and preventing shorts, thus improving the reliability and integrity of MRAM devices.
Implementation Method 1
The etch resistant dielectric layer, which may comprise amorphous carbon or carbon nitride, has a chemical bond energy or binding energy greater than the first dielectric layer
Data Source
AI summary
A semiconductor structure includes a bottom electrode, a magnetic tunneling junction stack over the bottom electrode, a top electrode over the magnetic tunneling junction stack, a first dielectric layer under the bottom electrode, a second dielectric layer under the first dielectric layer. The first dielectric layer has a first chemical bond energy and the second dielectric layer has a second chemical bond energy less than the first chemical bond energy.