MRAM Memory Pillar Dielectric Retention via Liner Recess
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for manufacturing semiconductor devices, particularly MRAM devices, face challenges in maintaining sufficient dielectric thickness during etching processes, which can lead to exposure of conductive layers and issues like shorts or opens due to the lack of sufficient dielectric coverage around memory pillars.
Innovation Solution
A method involving the deposition of a liner on an intermediate device with a sacrificial dielectric layer, followed by the selective removal of the liner and dielectric to form metallic tunnel junction stacks, while preserving the dielectric thickness, using techniques like chemical mechanical polish (CMP) elimination and selective wet etching to maintain the nitrogen doped silicon carbide layer thickness, and patterning with Ion Beam Etch (IBE) to form a stable MRAM structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Ion Beam Etch (IBE) is used to pattern metallic tunnel junctions, then etching precision is improved, but dielectric thickness is reduced leading to exposure of conductive layers
Solution Approach 1:
A liner layer is deposited on the sacrificial dielectric layer before the IBE process. This preliminary action protects the dielectric from excessive etching, preventing copper exposure while allowing the IBE to successfully pattern the MTJ with high precision.
Solution Approach 2:
The liner acts as an intermediary layer between the IBE process and the sacrificial dielectric. It absorbs the aggressive etching action, allowing the IBE to pattern the MTJ without directly damaging the dielectric thickness.
2Reliability
If the thickness of the surrounding dielectric is increased, then dielectric coverage is improved, but filling of high aspect microstuds becomes difficult
Solution Approach 1:
Instead of uniformly increasing dielectric thickness throughout, the solution applies a localized liner layer only where needed (on the sacrificial dielectric and in the opening). This provides enhanced dielectric coverage at critical interfaces while maintaining manageable aspect ratios for microstud filling.
3Manufacturing precision
If a liner is deposited and then removed by CMP, then manufacturing precision is improved, but dielectric thickness is reduced
Solution Approach 1:
The liner removal step is entirely eliminated from the process. The liner is left in place to serve as a protective layer throughout subsequent processing, extracting the need for CMP removal while maintaining its beneficial protective function.
Solution Approach 2:
The liner serves multiple functions: it protects the sacrificial dielectric during IBE, acts as a barrier during MTJ formation, and eliminates the need for CMP removal. This multi-functionality replaces the traditional deposit-and-remove approach with a keep-and-protect approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively preserves the dielectric thickness around memory pillars, preventing exposure of conductive layers and enhancing the reliability of MRAM devices by maintaining sufficient dielectric coverage during etching, thus reducing the risk of shorts or opens.
Implementation Method 1
removing a first portion of the liner by etching, wherein the liner is recessed into the opening
Implementation Method 2
Ion Beam Etch (IBE) is typically used to pattern metallic tunnel junctions (MTJs)
Implementation Method 3
depositing a plurality of metallic tunnel junction layers
Data Source
AI summary
A method of manufacturing a magnetic random access memory device includes depositing a liner on an intermediate device including an opening in a sacrificial dielectric layer, depositing a conductive metal over the liner and in the opening, removing a portion of the conductive metal while preserving the liner and a thickness of the sacrificial dielectric layer, removing a first portion of the liner by etching, wherein the liner is recessed into the opening, depositing a plurality of metallic tunnel junction layers, forming a hardmask on the plurality of metallic tunnel junction layers, and patterning the metallic tunnel junction layers to form a metallic tunnel junction stack and simultaneously clear a second portion of the liner and a portion the sacrificial dielectric layer.