MRAM Power Generator Segmentation for Low-Power Self-Refresh
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Solution Overview
Problem
Existing semiconductor storage devices, such as DRAM, consume high power during self-refresh operations, which accounts for a significant portion of mobile device operating time, and replacing them with nonvolatile MRAM does not significantly reduce power consumption when applied to volatile memory standards like LPDDR2.
Innovation Solution
The semiconductor storage device incorporates a power generator and command/address receiver that transition into specific power saving modes, including a third mode where the memory cell array is inactive and only the power generator is active, utilizing refresh commands that are unnecessary for nonvolatile MRAM to achieve low power consumption and high-speed recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If volatile memory (DRAM) uses self-refresh operations to maintain data, then data retention is achieved, but power consumption increases significantly
Solution Approach 1:
The patent changes the operational parameters by transitioning from volatile memory requiring continuous refresh to non-volatile memory that maintains data without refresh operations. The memory device implements multiple power saving modes (first, second, and third modes) with different active/inactive states of the memory cell array and power generator, allowing the system to operate at lowest power when data retention does not require refresh operations.
2Use of energy by moving object
If non-volatile MRAM is used to replace DRAM, then power consumption should reduce, but recovery speed from power saving mode may be insufficient
Solution Approach 1:
The patent segments the power saving modes into three distinct states with different levels of activity: first power saving mode (both array and generator inactive), second power saving mode (array inactive, generator active), and third power saving mode (array active, generator inactive). This segmentation allows the system to optimize between power consumption and recovery speed by selecting appropriate modes based on operational requirements.
Solution Approach 2:
The patent implements preliminary actions by keeping the power generator in an active state during second and third power saving modes, so that when data read operations are needed, the power generation capability is already ready. This preliminary maintenance of critical components reduces the recovery time from power saving modes to operational modes.
3Use of energy by moving object
If multiple power saving modes are implemented, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality by designing a unified control mechanism that handles multiple power saving modes through a single controller. The controller receives commands to transition between different power saving modes and manages the active/inactive states of both the memory cell array and power generator, consolidating what would otherwise be separate control systems into one integrated unit.
Data Source
AI summary
A memory includes a cell array including nonvolatile memory cells. A power generator generates a power supply voltage for driving the cell array. A receiver receives a command and an address. A controller controls an active state of the cell array, the power generator, and the receiver. In an activation mode, the cell array, the power generator, and the receiver are turned into the active states. In a first power saving mode, the cell array, the power generator, and the receiver are turned into inactive states. In a second power saving mode, the cell array and the power generator are turned into the active states, and the receiver is turned into the inactive state. In a third power saving mode, at least a part of the power generator is turned into the active state, and the cell array and the receiver are turned into the inactive states.