MRAM Programming Method Continuous Bit Line Voltage

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Solution Overview

Problem

Magnetic random access memory (MRAM) devices face a high write error rate due to manufacturing process issues, which limits the yield and reliability of nonvolatile semiconductor memory devices, despite increased write voltage.

Innovation Solution

A programming method for MRAM devices that involves maintaining bit line and source line voltages continuously through both program operations, allowing for extended programming time and reducing the write error rate by eliminating the need for voltage ramp-up time between operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If write voltage is increased to reduce write error rate, then reliability improves, but manufacturing defects increase causing write error rate to remain high

Engineering Contradiction:
Improvewrite error rateVSAvoiddefective memory cells
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by maintaining bit line and source line voltages at programming levels before the actual program operation begins. This pre-charging eliminates the voltage ramp-up time during programming, providing immediate high voltage stress to the memory cell to overcome manufacturing defects and reduce write error rates.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by continuously maintaining the bit line and source line at programming voltages throughout the programming period, including during intervals between word line pulses. This continuous voltage application ensures sustained programming effect without interruption, improving reliability despite manufacturing variations.

Inventive Principle:
Principle #20Continuity of useful action

2Productivity

If voltage is applied continuously to reduce programming time, then productivity improves, but energy consumption increases

Engineering Contradiction:
Improveprogramming timeVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent uses preliminary action by pre-charging the bit line and source line to programming voltages before word line activation. This eliminates the need for slow voltage ramp-up during each programming cycle, significantly reducing programming time while the energy is efficiently utilized during the active programming window.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs periodic action by applying word line pulses in periodic intervals while maintaining continuous bit line and source line voltages. This allows the memory cell to receive repeated programming stimuli without continuously charging the bit line and source line, reducing energy consumption while maintaining high programming speed.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly decreases the write error rate, improving the reliability and yield of MRAM devices by utilizing the time typically spent on voltage charging for additional programming, thereby enhancing the overall performance of the memory device.

Implementation Method 1

A representative example of such a nonvolatile element is a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) layer

Methodology Applied
Scientific EffectSpin transfer torque (STT):

Implementation Method 2

a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) layer

Methodology Applied
Scientific EffectTunneling magneto-resistive (TMR) effect: Magnetoresistance

Data Source

PatentUS10672447B2Memory device and programming method
Publication Date: 2020.06.02 SAMSUNG ELECTRONICS CO LTD
  • US10672447B2 patent drawing
  • US10672447B2 patent drawing
  • US10672447B2 patent drawing

AI summary

Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.