Common-Gate MRAM Read Amplifier for Weak Cell Signal Sensing

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Solution Overview

Problem

MRAM technologies face challenges in sensing the difference between low and high resistance states of memory cells due to signal attenuation from the middle of the memory array to the sense amplifier circuit, making it difficult to distinguish small voltage differences.

Innovation Solution

A common-gate amplifier circuit is inserted between the bit line and the sense amplifier circuit to amplify the voltage difference at the input, using a p-channel transistor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a sense amplifier circuit is used to detect voltage differences across MRAM memory cells, then the ability to read memory states is enabled, but signal attenuation occurs when reading from the middle of the memory array, making it difficult to distinguish small voltage differences

Engineering Contradiction:
Improvevoltage difference detection accuracyVSAvoidsignal attenuation
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

A common-gate amplifier circuit is introduced as an intermediary component between the bit line and the sense amplifier circuit. This amplifier circuit receives the attenuated voltage signal from the memory cell, amplifies it to restore the voltage difference magnitude, and then delivers the strengthened signal to the sense amplifier. This mediator approach directly addresses the signal attenuation problem by recovering the weakened signal before it reaches the detection circuit.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the voltage difference signal is amplified to improve detection accuracy, then measurement precision improves, but device complexity increases due to the additional amplifier circuit

Engineering Contradiction:
Improvevoltage difference detection accuracyVSAvoidcircuit structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The common-gate amplifier circuit is designed to serve multiple functions simultaneously: it amplifies the voltage signal, provides impedance matching between the memory cell and sense amplifier, and protects the sense amplifier from direct connection to the bit line. By making this single component multi-functional, the design achieves signal amplification without proportionally increasing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If a common-gate amplifier circuit is inserted between the bit line and sense amplifier circuit, then voltage difference is amplified, but the amplifier circuit itself consumes additional power

Engineering Contradiction:
Improvevoltage difference detection accuracyVSAvoidamplifier circuit power consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The common-gate amplifier circuit is designed with specific parameter optimizations including adjusted gain values, optimized biasing conditions, and careful selection of transistor dimensions to minimize power consumption while achieving sufficient amplification. The amplifier is configured to provide just enough gain to compensate for signal attenuation, avoiding excessive power consumption that would result from over-amplification.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260004833A1Apparatus and methods for amplifier circuits for reading MRAM memory cells
Publication Date: 2026.01.01 SANDISK TECHNOLOGIES LLC
  • US20260004833A1 patent drawing
  • US20260004833A1 patent drawing
  • US20260004833A1 patent drawing

AI summary

An apparatus includes a memory cell including a magnetic memory element coupled in series with a selector element, the memory cell including a first terminal coupled to a word line driver circuit and a second terminal coupled to a bit line driver circuit, and an amplifier circuit comprising an input terminal coupled to the bit line driver circuit, and an output terminal coupled to a current source configured to conduct a read current. The amplifier circuit is configured to amplify a voltage that is based on a difference between a first voltage across the memory cell and a second voltage across the memory cell.