Read Transistor Pre-Charges MRAM Bit Lines to Suppress Read Disturb

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Solution Overview

Problem

Resistance change type memory devices, such as MRAMs, face challenges in preventing read disturb due to large read currents that can invert the magnetization in storage layers, leading to instability and noise interference during operations.

Innovation Solution

Incorporating a read transistor between the clamp transistor and the global bit line, which pre-charges the nodes before the read operation and electrically separates the clamp transistor from the global bit line during write operations, to control and stabilize the read current and reduce noise interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If read current is increased to improve read speed, then reading efficiency is improved, but read disturb occurs due to magnetization inversion in storage layer

Engineering Contradiction:
Improveread speedVSAvoiddata stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The clamp transistor pre-charges the bit line to a predetermined voltage level before the read operation begins. This preliminary charging action ensures that when the read current flows through the memory cell, the voltage at the storage layer remains controlled and does not cause magnetization inversion, thereby preventing read disturb while maintaining adequate read current for fast operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The clamp transistor acts as an intermediary component between the bit line and the memory cell array. It mediates the read current by controlling the voltage level on the bit line, allowing sufficient current to flow for fast reading while preventing excessive voltage that would cause magnetization inversion and data instability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If read transistor is added to control read current, then read disturb is suppressed, but device complexity increases

Engineering Contradiction:
Improveread stabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The clamp transistor serves multiple functions: it pre-charges the bit line before read operations, controls the voltage level during reads to prevent magnetization inversion, and can be controlled to isolate or connect different circuit sections. This multi-functionality allows a single component to address read stability issues without proportionally increasing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively suppresses read disturb by maintaining stable read currents within the desired threshold, reducing the impact of noise and allowing for faster operational sequences while minimizing chip size and costs.

Implementation Method 1

An MRAM (Magnetoresistive Random Access Memory) is a memory device using, as memory elements, elements that utilize the magnetoresistive effect

Methodology Applied
Scientific EffectMagnetoresistive effect: Magnetoresistance

Implementation Method 2

a write current to apply a spin transfer torque to the storage layer so as to change a magnetization direction of the storage layer

Methodology Applied
Scientific EffectSpin transfer torque:

Data Source

PatentUS10410706B2Resistance change type memory
Publication Date: 2019.09.10 KIOXIA CORP
  • US10410706B2 patent drawing
  • US10410706B2 patent drawing
  • US10410706B2 patent drawing

AI summary

A memory includes a bit line connected to a memory cell and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell, a first transistor to control a current supplied to the memory cell based on a first control signal, and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.