Dynamic Redundancy Registers for MRAM Write Error Mitigation
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Solution Overview
Problem
Conventional STT-MRAM devices lack structures to track write errors and manage power consumption, leading to unreliable memory due to high write error rates and the absence of safeguards against overflow in error tracking structures.
Innovation Solution
The implementation of dynamic redundancy registers in STT-MRAM devices, which include an e1 register for storing data words and associated addresses, allowing for verification, re-write operations, and relocation without loss of throughput or speed, with optional e2 registers for non-volatile backup and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic redundancy registers are added to track write errors and enable re-write operations, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a hierarchical register structure where e1 registers are nested within memory banks and e2 registers provide an outer layer of redundancy. This nested arrangement allows error tracking and re-write operations to be integrated into the existing memory architecture without requiring completely separate error management systems, thereby improving reliability while controlling the increase in device complexity.
Solution Approach 2:
The e1 and e2 registers serve as intermediary structures between the memory bank and the control logic. These registers act as buffers that track write errors and manage re-write operations, isolating the complexity of error management from both the memory cells and the control unit. This intermediary approach enables reliable error handling while keeping the overall system architecture manageable.
2Reliability
If e1 and e2 registers are used to store and backup data words, then data integrity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different quality levels to different parts of the register system. The e1 registers, which handle active error tracking and re-write operations, are implemented with higher precision requirements. The e2 registers, which provide non-volatile backup, use different implementation techniques optimized for their specific function. This localized quality approach allows data integrity to be improved while avoiding uniform high precision requirements across all registers, thereby reducing overall manufacturing complexity.
3Productivity
If verify operations are performed simultaneously with write operations on the same row, then productivity is improved, but noise interference increases
Solution Approach 1:
The patent segments the memory bank into multiple independent rows that can be accessed simultaneously. By distributing verify and write operations across different row segments, the system achieves high productivity through parallel operations while minimizing noise interference. The segmentation ensures that bit-line coupling noise from one row does not affect verify operations in other rows, allowing simultaneous operations without significant noise penalties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables STT-MRAM devices to operate reliably with high write error rates by transparently handling re-write operations and maintaining data integrity, even during power down, through efficient error management and power utilization.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetization of the two layers
Implementation Method 2
one of the plates has its magnetization pinned (i.e., a 'reference layer'), meaning that this layer has a higher coercivity than the other layer
Implementation Method 3
this layer has a higher coercivity than the other layer and requires a larger magnetic field or spin-polarized current to change the orientation of its magnetization
Implementation Method 4
The cell's resistance will be different for the parallel and anti-parallel states and thus the cell's resistance can be used to distinguish between a '1' and a '0'
Data Source
AI summary
A method of writing data utilizes a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method also comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification. Additionally, the method comprises searching for at least one data word that is awaiting write verification in the error buffer, wherein verify operations associated with the at least one data word occur in a same row as the write operation. Finally, the method comprises determining if an address associated with any of the at least one data word is proximal to an address for the write operation and preventing a verify operation associated with the at least one data word from occurring in a same cycle as the write operation.