MRAM Reference Cell Configuration for Accurate Resistance Sensing
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Solution Overview
Problem
Existing methods for discerning logic levels in magnetic memory elements, such as STT-MRAM, face challenges in accurately reading resistance states due to manufacturing variations and the risk of read-disturb errors, especially when using a fixed reference voltage that may not be optimal for all chips, leading to inaccuracies in determining whether a memory element is in a high or low resistance state.
Innovation Solution
The use of average resistance, voltage, or current values derived from reference MTJ elements in known high and low resistance states, coupled with a comparator, to determine the resistance state of a memory element, thereby avoiding read-disturb errors by maintaining reference elements in safe polarity orientations and using the same read bias current for both reference and memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed reference voltage is used for sensing resistance states, then the circuit design is simple, but measurement precision deteriorates due to manufacturing variations
Solution Approach 1:
The reference voltage is changed from a fixed value to a dynamic value that is adjusted based on actual manufacturing variations. The system dynamically adapts the reference voltage to match the specific chip's characteristics, resolving the contradiction between simple fixed-voltage design and accurate sensing under manufacturing variations.
Solution Approach 2:
The reference voltage parameter is made variable rather than fixed. By adjusting the reference voltage parameter according to measured resistance states and manufacturing variations, the system achieves accurate sensing across different chips while maintaining a relatively simple overall circuit architecture.
2Measurement precision
If a read bias current is applied to sense resistance states, then logic levels can be detected, but read-disturb errors occur in magnetic memory elements
Solution Approach 1:
The system uses an intermediary approach by applying read bias current not directly to the memory element being sensed, but to reference elements that are replicas of the memory elements. This intermediary sensing method allows logic level detection while protecting the actual memory elements from read-disturb errors.
Solution Approach 2:
The system creates copies (reference elements) of the memory elements and uses these copies for sensing operations. By copying the memory element structure and using the copy for resistance sensing, the system achieves accurate logic level detection without disturbing the original memory element's data state.
3Measurement precision
If reference elements are used to determine optimal reference voltage, then measurement precision improves, but device complexity increases
Solution Approach 1:
The reference elements serve multiple functions: they act as both memory elements and sensing references. By making the reference elements multi-functional, the system achieves improved measurement precision without proportionally increasing device complexity, as the same structures fulfill dual purposes.
Solution Approach 2:
The system merges the reference element functionality with the memory element structure. By combining the sensing reference function with the memory storage function in the same physical structures, the system achieves accurate sensing while minimizing additional circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a simple and accurate method to distinguish between high and low resistance states in magnetic memory elements, reducing the risk of read-disturb errors and optimizing the configuration of MTJ elements in the reference section, ensuring reliable logic value sensing across varying manufacturing conditions.
Implementation Method 1
A spin-transfer torque magneto-resistive random access memory (STT-MRAM) stores data values in storage elements having two superimposed layers of magnetic material separated by a thin insulating film, defining a magnetic tunnel junction or 'MTJ'.
Implementation Method 2
The two orientations are characterized by distinctly different serial resistances through the superimposed layers of the MTJ. The magnetic field orientation of the changeable layer can be aligned the same as that of the permanent magnet layer (parallel), or the magnetic field of the changeable layer can be aligned directly opposite to that of the permanent magnet layer (anti-parallel).
Implementation Method 3
For reading the logic value of an MTJ bit cell, a bias current is applied serially through the superimposed magnetic layers, causing a bit cell read voltage to be developed. Assuming that a same bias current amplitude is applied, a voltage amplitude is generated according to Ohm's Law, V=IR, that differs with the serial resistance through the MTJ and superimposed magnetic layers.
Data Source
AI summary
A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states RH and RL, providing a voltage, current or other parameter for comparison against the memory element to discern a resistance state. The parameter represents an intermediate resistance straddled by RH and RL, such as an average or twice-parallel resistance. The reference MTJ elements are biased from the same read current source as the memory element but their magnetic layers are in opposite order, physically or by order along bias current paths. The reference MTJ elements are biased to preclude any read disturb risk. The memory bit cell is coupled to the same bias polarity source along a comparable path, being safe from read disturb risk in one of its two possible logic states.