MRAM Cell With Rotated Gate Transistor
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Solution Overview
Problem
Conventional memory devices with thermally assisted switching magnetic random access memory (TAS-MRAM) cells face challenges in minimizing cell size and reducing power consumption due to the large size of select transistors required for high write bias voltages, leading to increased size and power consumption.
Innovation Solution
The memory device arrangement includes a magnetic tunnel junction and a select transistor, where the bit line connects to the drain of the select transistor, and the source line connects to the other end of the magnetic tunnel junction, allowing for smaller select transistors by applying specific bias voltages during write and read operations, minimizing heating current requirements and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TAS-MRAM cell configuration is used with select transistor connected to source line, then the magnetic tunnel junction can be switched, but the select transistor size becomes large requiring high write bias voltages, increasing cell size and power consumption
Solution Approach 1:
The patent inverts the conventional connection configuration by connecting the select transistor drain to the bit line and source to the magnetic tunnel junction, rather than the conventional source-to-source line connection. This inversion changes the voltage distribution and current path, allowing the magnetic tunnel junction to receive adequate switching voltage while the select transistor operates with lower overdrive voltage, thus reducing its required size.
Solution Approach 2:
The patent changes the voltage parameters applied to different lines during write and read operations. By applying specific voltage combinations (e.g., Vdd to bit line and word line during write, 0V to bit line and Vdd to word line during read), the patent optimizes the voltage across the magnetic tunnel junction for switching while limiting the voltage across the select transistor, enabling smaller transistor dimensions.
2Reliability
If high write bias voltages are applied to ensure adequate voltage across magnetic tunnel junction, then the junction can be switched reliably, but the select transistor size must increase to handle the voltage, increasing overall cell size
Solution Approach 1:
The inverted connection configuration allows the magnetic tunnel junction to be positioned in a circuit path where it receives the full voltage swing needed for reliable switching, while the select transistor is positioned to operate with optimized voltage conditions that reduce its required channel length and width.
Solution Approach 2:
The patent segments the voltage application function across different lines (bit line, word line, source line) with different voltage levels applied during write and read operations. This segmentation allows the magnetic tunnel junction to receive high voltage for switching while the select transistor operates under optimized voltage conditions, reducing its size requirements.
3Reliability
If larger select transistors are used to handle write bias voltages, then adequate voltage can be applied across magnetic tunnel junction, but power consumption increases due to larger transistor leakage and operating current
Solution Approach 1:
The patent changes the voltage parameters applied to bit lines, word lines, and source lines during different operations. By applying Vdd to bit line and word line during write (with source line at 0V), and reversing during read operations, the patent ensures adequate voltage across the magnetic tunnel junction while the select transistor operates with optimized voltage conditions that reduce both dynamic and leakage power consumption.
Solution Approach 2:
The inverted connection configuration reduces the voltage stress on the select transistor, allowing it to be sized smaller with lower leakage current. The magnetic tunnel junction still receives adequate voltage for switching because of its position in the inverted circuit configuration, thus reducing overall power consumption while maintaining reliability.
4Ease of operation
If conventional connection arrangement is used, then the circuit can operate, but parasitic currents increase due to larger transistor size and higher operating voltages
Solution Approach 1:
The patent changes the voltage parameters applied to different lines during write and read operations. By applying specific voltage combinations (Vdd to bit line and word line during write, 0V to bit line and Vdd to word line during read), the patent minimizes voltage across non-selected transistors and reduces parasitic leakage currents while maintaining adequate voltage for selected cell operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the use of smaller select transistors, reducing the overall size of the memory device while achieving high density and low power consumption, with reduced parasitic currents and minimized power usage compared to conventional devices.
Implementation Method 1
Each TAS-MRAM cell 1 comprises a magnetic tunnel junction represented by the numeral 2
Implementation Method 2
a second antiferromagnetic layer (also not shown) pinning the storage layer when the magnetic tunnel junction 2 is at a temperature that is below a critical temperature of the second antiferromagnetic layer
Implementation Method 3
The write bias voltage Vmtj must be high enough to pass a heating current 31 through the magnetic tunnel junction 2 capable of heating the TAS-MRAM cell 1 above the critical temperature of the antiferromagnetic layer
Implementation Method 4
passing a spin transfer torque current (not shown) through the magnetic tunnel junction 2, via the activated bit line BL, the storage layer magnetization being then switched by the so-called spin transfer torque (STT) effect
Data Source
Figure 1a
Figure 1b
Figure 2a
AI summary
A memory device (10) comprising a plurality of magnetoresistive random access memory (MRAM) cells (1) arranged in rows and columns, each MRAM cell (1) comprising a magnetic tunnel junction (2) and a select transistor (3); a plurality of word lines (WL), each word line (WL) connecting MRAM cells (1) along a row via the gate of their select transistor 3; a plurality of bit lines (BL), each bit line (BL) connecting MRAM cells (1) along a column; and a plurality of source lines (SL), each source line (SL) connecting MRAM cells (1) along a row; characterized in that one end of the magnetic tunnel junction (2) being electrically coupled to the source of the select transistor (3); each bit line (BL) connecting the MRAM cells (1) via the drain of their select transistor 3; and each source line (SL) connecting the MRAM cells (1) via the other end of the magnetic tunnel junction (2). The disclosed memory device has a decreased size and lower power consumption compared with conventional memory devices.