MRAM Upper Electrode Exposure via Sacrificial Layer
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Solution Overview
Problem
During the manufacturing of magnetoresistive random access memory (MRAM) devices, the chemical mechanical polishing (CMP) process can lead to electrical short-circuiting of magnetic tunnel junction (MTJ) patterns due to over-etching of upper electrodes, resulting in poor device characteristics.
Innovation Solution
A method involving the formation of a protective layer structure with a capping layer, sacrificial layer, and etch stop layer, followed by selective etching to expose the upper electrode, allowing for the formation of wiring without the need for CMP, thereby preventing electrical short-circuiting and improving alignment margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to expose upper electrode, then upper electrode can be exposed for wiring formation, but upper electrode may be over-etched and removed causing MTJ pattern electrical short-circuiting
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary between the upper electrode and the etching process. This sacrificial layer is selectively removed to expose the upper electrode for wiring formation, while the upper electrode itself is protected from direct etching that would cause over-etching and electrical short-circuiting of the MTJ pattern.
Solution Approach 2:
The patent applies preliminary protective action by forming a protective layer structure (including capping layer, sacrificial layer, and etch stop layer) before the etching process. This preliminary structure prevents harmful over-etching during the exposure of the upper electrode, ensuring the upper electrode remains intact for subsequent wiring formation.
2Ease of manufacture
If CMP process is used to expose upper electrode, then wiring can be formed on upper electrode, but alignment margin is reduced due to over-etching
Solution Approach 1:
The sacrificial layer acts as a mediator that enables wiring formation on the upper electrode while maintaining precise alignment. By selectively removing the sacrificial layer rather than directly etching the upper electrode, the process preserves the upper electrode's dimensions and position, ensuring proper alignment margins for wiring formation.
Solution Approach 2:
The sacrificial layer is a temporary, disposable structure that is removed after serving its protective function. This temporary layer enables precise exposure of the upper electrode for wiring formation without permanently affecting the upper electrode's dimensions or alignment, thus maintaining manufacturing precision while enabling ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents electrical short-circuiting of MTJ structures and enhances the manufacturing process by allowing for the formation of MRAM devices with improved characteristics and increased alignment margins without the use of CMP.
Implementation Method 1
an anisotropic etching process may be performed on the etch stop layer, so that portions of the etch stop layer except for a portion of the etch stop layer on a sidewall of the memory unit may be removed
Implementation Method 2
When the exposed portion of the sacrificial layer is removed to expose the portion of the capping layer, a wet etching process may be performed
Implementation Method 3
When the exposed portion of the capping layer is removed to expose the upper electrode, a wet etching process may be performed
Implementation Method 4
when the insulating interlayer is partially removed to form the opening exposing the protective layer structure, a dry etching process may be performed
Data Source
AI summary
In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.


