MRAM Segment Control for Burst Length and Power
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Solution Overview
Problem
Nonvolatile MRAMs face challenges in increasing burst length and data volume due to high power consumption when activating multiple global word lines, which limits their data reading and writing capabilities compared to DRAMs.
Innovation Solution
The MRAM design incorporates a plurality of local word lines and bit lines with shared global word lines, where segment controllers and address decoders selectively drive local word lines and bit lines to enable independent operation of memory segments, allowing for pipeline-controlled data access without continuous activation of global word lines, thereby increasing burst length and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple global word lines are activated to increase burst length, then data volume increases, but power consumption increases
Solution Approach 1:
The memory array is divided into multiple memory segments, each with its own local word lines and bit lines. This segmentation allows independent access to different segments without activating all global word lines simultaneously, enabling increased data volume through sequential segment access while reducing overall power consumption.
Solution Approach 2:
The patent implements pipeline-controlled data access where memory segments are accessed in a periodic, alternating manner. While one segment is being accessed, another segment can be prepared or transferred data, creating a periodic access pattern that increases effective data volume without requiring continuous activation of multiple global word lines.
2Productivity
If multiple global word lines are activated to increase burst length, then access rate improves, but power consumption increases
Solution Approach 1:
Pipeline control enables alternating access patterns between multiple memory segments, where data transfer from one segment occurs simultaneously with preparation or access in another segment. This periodic action maintains high access rates by keeping the data path continuously utilized without requiring multiple global word lines to remain active simultaneously.
Solution Approach 2:
The patent ensures continuous useful action by implementing pipelined data transfer where while one memory segment is being accessed, another segment is being prepared or its data is being transferred out. This continuity maintains high productivity without the need for continuous activation of multiple global word lines, as each segment is accessed sequentially but without idle time in the data path.
3Measurement precision
If sense amplifier area is increased to detect minute current, then reading capability improves, but device area increases
Solution Approach 1:
The patent employs a current mirror circuit where the sense amplifier's own output current is mirrored to generate a comparison current. This self-service mechanism enables the sense amplifier to detect minute current differences from memory cells without requiring external reference circuits, maintaining high reading capability while minimizing the addition of external circuitry area.
Solution Approach 2:
The sense amplifier circuit integrates multiple functions including current amplification, current mirroring, and data latching within a single unified circuit block. By merging these functions that could otherwise be separate circuits, the patent achieves precise reading capability while minimizing the total device area occupied by sense amplifier infrastructure.
Data Source
AI summary
A semiconductor storage device according to the present embodiment includes local word lines and bit lines intersecting the local word lines. Each memory segment includes nonvolatile memory cells. Each memory segment corresponds to a plurality of the local word lines. A sense amplifier corresponds to a plurality of the bit lines. A global word line corresponds to a plurality of the local word lines, and is commonly driven in the memory segments. A decoder is connected between the global word line and the local word lines corresponding to the global word line, and selectively drives a certain local word line from the local word lines. A segment controller is provided in each memory segment, and selects one of the memory segments to be driven. An input/output part outputs read data from the memory segments or receives write data to the memory segments.