MRAM Memory System Segmentation for Speed and Capacity
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving both high-speed processing and large capacity processing within a single memory system, as existing memory technologies require different materials and processes for high-speed operation and large capacity integration, leading to increased manufacturing costs and complexity.
Innovation Solution
A semiconductor device is designed with a combination of current-induced magnetic field write type MRAM for high-speed operation and spin-polarized current write type MRAM for large capacity and high integration, both integrated on the same chip using the same process, allowing for efficient data storage and reduced manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current-induced magnetic field write type MRAM is used for high-speed operation, then writing speed is improved (1 nanosecond or less), but write current increases (about 1 mA or more) and chip area increases
Solution Approach 1:
The invention segments the memory system into two distinct MRAM types: one optimized for high-speed operation using current-induced magnetic field write method, and another optimized for low-power operation using spin-polarized current write method. This segmentation allows each memory type to specialize in its respective function without compromise, resolving the contradiction between speed and power consumption by distributing different operational requirements to different memory components.
2Use of energy by moving object
If spin-polarized current write type MRAM is used for large capacity and high integration, then write current is reduced (enabling scaling), but writing speed decreases (1 nanosecond or more)
Solution Approach 1:
The memory system is divided into two functional segments: high-speed MRAM for performance-critical applications and high-integration MRAM for capacity-critical applications. This segmentation enables the high-integration MRAM to use spin-polarized current write method with lower write current and better scaling, while the high-speed MRAM handles time-sensitive operations, thus resolving the speed-power tradeoff through functional separation.
3Adaptability or versatility
If different types of memories are used for high-speed operation and large capacity integration, then both performance requirements are met, but manufacturing complexity increases (different materials and processes)
Solution Approach 1:
The invention employs a universal magnetic tunnel junction (MTJ) structure and common fabrication process for both high-speed MRAM and high-integration MRAM. By using the same base technology platform (MTJ cells with pinned layers and free layers) and manufacturing processes, the system achieves multi-functionality while maintaining manufacturing simplicity. The differentiation between the two memory types is achieved through structural variations rather than fundamentally different materials or processes.
Solution Approach 2:
While maintaining a universal manufacturing process, the invention applies local quality variations in the form of different MTJ structural configurations for different memory functions. The high-speed MRAM uses one MTJ structure optimized for speed, while the high-integration MRAM uses another MTJ structure optimized for density, allowing each region to have locally optimized properties while being manufactured through the same overall process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a nonvolatile memory system that achieves both high-speed processing and large capacity processing, reducing power consumption and manufacturing costs while simplifying the manufacturing process by using the same materials and processes for different types of MRAMs.
Implementation Method 1
a magneto-resistance effect element is integrated in a memory cell and data is stored as orientation of magnetization of a ferromagnetic layer in the magneto-resistance effect element
Implementation Method 2
the magnetization direction of the ferromagnetic layer in the magneto-resistance effect element is switched by a current magnetic field that occurs due to the passage of the write current
Implementation Method 3
magnetization is switched due to a direct interaction between spin of conduction electrons that bear the current and a magnetic moment of the conductor
Data Source
AI summary
A semiconductor device includes: a first magnetic random access memory including a first memory cell and a second magnetic random access memory including a second memory cell operating at higher speed than the first memory cell and is provided on the same chip together with the first magnetic random access memory. The first memory cell is a current-induced domain wall motion type MRAM and stores data based on a domain wall position of a magnetization free layer. A layer that a write current flows is different from a layer that a read current flows. The second memory cell is a current-induced magnetic field writing type MRAM and stores data based on a magnetic field induced by a write current.