MRAM Selector Threshold Voltage Segmentation for Latency and Capacity Trade-offs
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Solution Overview
Problem
Current memory devices using magnetoresistive random access memory (MRAM) face challenges in optimizing both performance and storage capacity due to the limitations of selector threshold voltages, which affect read and write operations and power consumption.
Innovation Solution
The memory device employs two types of memory matrices with selectors having different threshold voltages, allowing for optimized performance in one matrix and increased storage capacity in another, by varying the arsenic concentration in the silicon oxide films of the selectors and adjusting their thicknesses to suit specific memory cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single type of memory matrix with uniform selector threshold voltage is used, then the device structure is simple and manufacturing is easier, but both performance and storage capacity cannot be simultaneously optimized
Solution Approach 1:
The memory device is divided into multiple memory matrices (first memory matrix and second memory matrix) with different selector threshold voltages. The first memory matrix uses selectors with first threshold voltages optimized for performance, while the second memory matrix uses selectors with second threshold voltages optimized for storage capacity, allowing each segment to serve its specific function optimally
Solution Approach 2:
Different regions of the memory device are assigned different selector threshold voltage characteristics. The first memory matrix region has selectors with higher threshold voltages for better performance, while the second memory matrix region has selectors with lower threshold voltages for increased capacity, creating local optimization throughout the device
2Productivity
If selector threshold voltage is increased to improve performance, then read and write operations are optimized, but storage capacity is limited
Solution Approach 1:
The memory device is segmented into multiple matrices with different threshold voltage characteristics. The first memory matrix uses selectors with higher threshold voltages to achieve fast access performance, while the second memory matrix uses selectors with lower threshold voltages to enable higher storage capacity, allowing both requirements to be met simultaneously in different segments
3Quantity of substance
If selector threshold voltage is decreased to increase storage capacity, then more memory cells can be stored, but access performance deteriorates and power consumption increases
Solution Approach 1:
The memory device is divided into multiple matrices where the second memory matrix uses selectors with lower threshold voltages to achieve increased storage capacity, while the first memory matrix uses selectors with higher threshold voltages to maintain fast access performance and lower power consumption for performance-critical operations
4Ease of manufacture
If uniform selector threshold voltage is used across all memory matrices, then manufacturing process is simplified, but chip performance cannot be maximized
Solution Approach 1:
Different regions of the chip are assigned different selector threshold voltage characteristics to optimize local performance. The first memory matrix region has selectors with higher threshold voltages for fast access, while the second memory matrix region has selectors with lower threshold voltages for high capacity, maximizing overall chip performance through local optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances access performance, reduces power consumption, and maximizes chip performance by balancing latency, storage capacity, and endurance across different memory matrices.
Implementation Method 1
A memory device which adopts a magnetoresistance effect element as a memory element is known
Data Source
AI summary
A memory device includes a memory cell array, first and second memory cells, first and second read circuits, and first and second write circuits. The memory cell array includes first and second sub-arrays. The first memory cells are included in each of the first sub-arrays. The second memory cells are included in each of the second sub-arrays. The first and second read circuits are provided for reading data of the first and second memory cells, respectively. The first and second write circuits are provided for writing data to the first and second memory cells, respectively. An area of the first sub-array is different from an area of the second sub-array.