MRAM Cell Single Crystal Self-Aligned Diode Size Reduction
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Solution Overview
Problem
Current MRAM cells face challenges in achieving small size and simple fabrication processes, with single crystal diodes being difficult to shrink and poly-crystal diodes experiencing current leakage, while transistors have complex fabrication and larger sizes.
Innovation Solution
A magnetic random access memory (MRAM) cell is developed using a single crystal self-aligned diode with a bottom implant region and a contact implant region, where the contact implant region is surrounded by the bottom implant region except for one side, and metal silicide lines are used to define the size of the diode, along with specific fabrication and programming methods for in-plane and perpendicular magnetization directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single crystal diode is used as the selective device, then the device structure is simple, but it is difficult to shrink the size
Solution Approach 1:
The patent transitions from planar diode structures to vertically stacked three-dimensional structures. The selective device is formed as a vertical stack with alternating semiconductor layers and conductive layers, extending in the vertical dimension rather than expanding horizontally. This allows the diode to maintain its structural simplicity while achieving significant size reduction through the third dimension.
Solution Approach 2:
The patent implements a nested structure where multiple functional layers are stacked within a compact vertical space. The selective device contains nested layers including semiconductor layers, conductive layers, and insulating layers, each serving specific functions. This nesting approach allows the diode to maintain simplicity while minimizing the horizontal footprint by stacking functions vertically.
2Length of moving object
If a poly-crystal diode is used as the selective device, then the device size can be reduced, but current leakage occurs at the reverse bias region
Solution Approach 1:
The patent employs composite material structures with alternating semiconductor layers and conductive layers. The semiconductor layers provide the rectifying function while the conductive layers enhance electrical connectivity. This composite structure maintains the small size advantage of poly-crystal diodes while eliminating current leakage through the engineered material composition and interface design.
Solution Approach 2:
The patent modifies key parameters including the thickness of semiconductor and conductive layers, doping concentrations, and material compositions. By optimizing these parameters, the device achieves low reverse bias current leakage while maintaining small dimensions. The conductive layers with optimized thickness and material properties prevent leakage paths that would otherwise occur in poly-crystal structures.
3Reliability
If a transistor is used as the selective device, then current leakage is controlled, but the fabrication process becomes more complicated and device size increases
Solution Approach 1:
The patent extracts the essential current control function from the complex transistor structure and implements it through a simplified selective device. By removing unnecessary components and retaining only the critical rectifying and selecting functions, the device achieves reliable current leakage control without requiring complex multi-step transistor fabrication processes. The selective device uses a streamlined stack of semiconductor and conductive layers that can be integrated more simply into the MRAM cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MRAM cell achieves a small size and simple fabrication process, avoiding current leakage issues and complex transistor fabrication, while maintaining high integration density and efficient programming capabilities.
Implementation Method 1
a bottom implant (BI) region and a contact implant (CI) region. Having a first polarity, the BI region is defined in a silicon substrate. The CI region is defined in the portion of the silicon substrate that is within the BI region such that the CI region is surrounded by the BI region except for a side of the CI region that aligns with the surface of the silicon substrate. The CI region has a second polarity that is opposite to the first polarity of the BI region.
Implementation Method 2
Formed by multi-layer ferromagnetic thin films, the MRAM device of a MRAM cell can have either in-plane or perpendicular magnetization directions relative to the surfaces of the ferromagnetic thin films. Because the resistance of the MRAM device changes according to the magnetization directions formed in the multi-layer ferromagnetic thin films, the information stored at the MRAM device of a MRAM cell is read by sensing current variations due to the resistance change.
Implementation Method 3
A first metal silicide line and a second metal silicide line are defined adjacent to the first spacer and the second spacer, respectively. The thickness of each of the first spacer and the second spacer defines the size of the single crystal self-aligned diode.
Data Source
AI summary
A magnetic random access memory (MRAM) cell comprises a MRAM device and a single crystal self-aligned diode. The MRAM device and the single crystal self-aligned diode are connected through a contact. Only one metal line is positioned above the MRAM device of the MRAM cell. A first and second spacers positioned adjacent to the opposite sidewalls of the contact define the size of the single crystal self-aligned diode. A first and second metal silicide lines are positioned adjacent to the first and second spacers, respectively. The single crystal self-aligned diode, defined in a silicon substrate, includes a bottom implant (BI) region and a contact implant (CI) region. The CI region is surrounded by the BI region except for a side of the CI region that aligns the surface of the silicon substrate. A fabrication method, a read method, two programming methods for the MRAM cell are also disclosed.