MRAM Electrode Structure for Self-Aligned MTJ Contact Formation
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Solution Overview
Problem
The challenge in fabricating MRAM devices is the misalignment of contact vias and top electrodes, leading to increased contact resistance and performance issues, particularly as IC dimensions decrease, which complicates the formation of common electrodes and results in higher costs and reduced yield.
Innovation Solution
A method involving the deposition of a first dielectric layer over a workpiece with a magnetic tunneling junction and a dummy top electrode, followed by a first planarization process that stops before exposing the top surface of the dummy electrode, allowing for the removal of the dummy electrode and deposition of an electrode layer, and a second planarization process to create a coplanar surface, simplifying the fabrication process and reducing fabrication costs while improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and etching processes are used to form common electrodes, then alignment precision can be improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent applies preliminary action by forming a dummy top electrode during the MTJ fabrication process itself, before the common electrode formation step. This dummy electrode serves as a placeholder that guides subsequent material deposition, eliminating the need for photolithography alignment while ensuring proper positioning of the common electrode.
Solution Approach 2:
The dummy top electrode acts as an intermediary element that mediates between the MTJ structure and the common electrode. It provides a physical reference during fabrication that simplifies the formation process, and is later removed after serving its guiding function, thereby reducing overall process complexity.
2Manufacturing precision
If photolithography and etching processes are used to form common electrodes, then alignment precision can be improved, but fabrication cost increases
Solution Approach 1:
The dummy top electrode is formed in advance during MTJ fabrication, serving as a built-in alignment reference that eliminates costly photolithography steps for common electrode formation, thereby reducing fabrication costs while maintaining alignment precision.
3Manufacturing precision
If photolithography and etching processes are used to form common electrodes, then alignment precision can be improved, but manufacturing yield decreases
Solution Approach 1:
The dummy top electrode provides a pre-established alignment reference that eliminates photolithography and etching steps, reducing process variability and residue defects, thereby improving manufacturing yield while maintaining alignment precision.
4Productivity
If IC dimensions are decreased to increase functional density, then productivity is improved, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The dummy top electrode serves as a physical placeholder formed during MTJ fabrication that guides common electrode material deposition, providing inherent alignment guidance that is particularly beneficial for scaled-down devices where photolithography alignment becomes increasingly difficult.
Solution Approach 2:
The dummy top electrode acts as an intermediary structure that simplifies the formation of common electrodes in scaled-down devices, providing a physical reference that maintains alignment precision even as device dimensions decrease and functional density increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication of MRAM devices by eliminating the need for photolithography and etching processes, reducing fabrication costs and improving yield by ensuring proper alignment and reducing residue defects, thus enhancing device performance.
Implementation Method 1
performing a second planarization process such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar
Implementation Method 2
depositing a first dielectric layer over the workpiece
Implementation Method 3
depositing an electrode layer to fill the opening
Data Source
AI summary
Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.