MRAM Top Via Formation Using Self-Aligned Hard Mask Planarization
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Solution Overview
Problem
The existing process flow for manufacturing magnetoresistive random access memories (MRAMs) faces challenges in forming top conductive via holes, as they require different sizes and depth-width ratios for the array and logic zones, making it difficult to achieve precise and efficient manufacturing.
Innovation Solution
A method is introduced that involves forming a prefabricated substrate structure with a hard mask material layer, where the top electrode and hard mask layers are photoetched and etched to create top electrodes and hard mask layers, followed by backfilling and selective removal of the hard mask layer to form via holes through self-alignment, allowing for independent formation of array and logic zone via holes, and subsequent metal filling and etching to create interconnection patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If top conductive via holes are formed by photomask at the same time for array zone and logic zone, then the process is simplified, but the manufacturing precision deteriorates due to different size and depth-width ratio requirements
Solution Approach 1:
The patent divides the via hole formation process into separate steps for array zone and logic zone. First, array zone top via holes are formed through self-aligned etching using the top electrode as mask, then logic zone top via holes are formed independently with different dimensions. This segmentation allows each zone to have optimized via hole parameters without compromising the other zone's precision requirements.
2Manufacturing precision
If different via hole formation methods are used for array zone and logic zone, then the manufacturing precision is improved, but the device complexity increases
Solution Approach 1:
The patent merges the formation of array zone top via holes and logic zone top via holes into a unified process flow. The top electrode and hard mask layer are formed simultaneously across the entire wafer, then selectively removed or retained based on zone requirements. This merging approach maintains high precision for both zones while avoiding the need for completely separate processing sequences.
3Measurement precision
If self-alignment method is used for array zone top via hole formation, then the alignment precision is improved, but the process complexity increases
Solution Approach 1:
The patent employs self-aligned etching where the top electrode itself serves as the etch mask for forming array zone top via holes. The top electrode pattern is directly transferred to the underlying layers without requiring additional alignment steps or separate mask layers. This self-service approach achieves high alignment precision while minimizing process complexity by eliminating redundant masking and alignment operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the precision and controllability of forming top interconnection structures in MRAMs, enhancing the in-plane uniformity and process window, allowing for simpler and more controllable manufacturing processes by utilizing the hard mask layer as a grinding and etching stop, resulting in better alignment and filling of via holes and interconnection lines.
Implementation Method 1
the top electrode material layer and the hard mask material layer are photoetched and etched to form at least one top electrode and at least one hard mask layer
Implementation Method 2
the top electrode material layer and the hard mask material layer are photoetched and etched to form at least one top electrode and at least one hard mask layer
Implementation Method 3
backfilling is conducted with a medium, and the backfilled medium is ground to be equal to each of the at least one hard mask layer in height by using each of the at least one hard mask layer as a grinding stop layer
Implementation Method 4
the at least one hard mask layer is selectively removed, and at least one array zone top via hole is formed through self-alignment
Data Source
AI summary
The disclosure provides a method for manufacturing a MRAM, wherein a prefabricated substrate structure is provided, on which at least one array zone bottom interconnection line, at least one bottom electrode and at least one magnetic tunnel junction, at least one logic zone bottom interconnection line, and a first medium layer are provided; a top electrode material layer and a hard mask material layer are formed on a surface of each of the at least one magnetic tunnel junction; the top electrode material layer and the hard mask material layer are photoetched and etched to form at least one top electrode and at least one hard mask layer; backfilling is conducted with a medium, and the backfilled medium is ground to be equal to the hard mask layer in height; the hard mask layer is selectively removed, and at least one array zone top via hole is formed through self-alignment.