MRAM Memory Cell With Semiconductor Interconnections
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in achieving a memory cell area of 4F2 with high-speed operation and low parasitic resistance, particularly in MRAMs, due to the unsuitability of semiconductor interconnections for large current requirements and the difficulty in forming Si single crystals on metal layers.
Innovation Solution
The implementation of a semiconductor memory device with a plane semiconductor layer as the lower interconnection, incorporating two selection transistors as vertical transistors and a magnetoresistive element, which allows for the formation of an MRAM with a memory cell area of 4F2 without the need for metal interconnections, reducing parasitic resistance and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If metal interconnections are used in MRAM, then current handling capability is improved, but device complexity and manufacturing difficulty increase due to the need for semiconductor substrate bonding techniques
Solution Approach 1:
The invention extracts and removes the metal interconnection layer from the MRAM structure, replacing it with a semiconductor-based interconnection system. This eliminates the need for complex semiconductor substrate bonding techniques while maintaining current handling capability through optimized semiconductor material and structure design.
Solution Approach 2:
The semiconductor layer serves multiple functions simultaneously: it acts as both the interconnection medium and the active device region. This multi-functionality eliminates the need for separate metal interconnection layers and bonding processes, simplifying the overall device structure and manufacturing while maintaining electrical performance.
2Device complexity
If semiconductor interconnections are used, then device complexity is reduced, but parasitic resistance increases affecting high-speed operation
Solution Approach 1:
The invention changes the physical and electrical parameters of the semiconductor interconnection by using highly doped semiconductor regions with optimized geometry. This reduces the resistivity and dimensional constraints of the semiconductor interconnection, thereby minimizing parasitic resistance while maintaining manufacturing simplicity.
Solution Approach 2:
The invention employs composite semiconductor structures with different doping levels and material compositions in different regions. This allows optimization of electrical properties (lower resistance) in interconnection regions while maintaining the necessary device functionality, effectively reducing parasitic resistance without complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the formation of an MRAM with a memory cell area of 4F2, achieving low parasitic resistance and reducing costs by eliminating the need for semiconductor substrate bonding techniques, while allowing for high-speed operation and efficient current handling.
Implementation Method 1
A spin-transfer torque MRAM (Magnetic Random Access Memory) including a magnetoresistive element containing a ferromagnetic material as a memory element has been proposed. This MRAM is a memory that stores data by controlling the electrical resistance of the magnetoresistive element to two states, i.e., a high-resistance state and low-resistance state by changing the magnetization direction in a magnetic layer by using a current to be supplied to the magnetoresistive element.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cells arranged in rows and columns; a source line electrically connected to one terminal of each of the memory cells; a bit line electrically connected to the other terminal of each of the memory cells; a plurality of first word lines, each electrically connected to memory cells included in corresponding one of the rows; and a plurality of second word lines, each electrically connected to memory cells included in corresponding one of the columns. Each of the memory cells includes a first selection transistor including a current path having one end electrically connected to the source line; a second selection transistor including a current path having one end electrically connected to the other end of the current path of the first selection transistor; and a variable resistance element including a current path having one end electrically connected to the other end of the current path of the second selection transistor, and the other end electrically connected to the bit line.