MRAM Cell Structure With Shared MTJ Pads for High Memory Density
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Solution Overview
Problem
Existing MRAM technologies face a challenge in maintaining high memory density while utilizing multiple transistors to drive Magnetic Tunnel Junctions (MTJs, as this occupation of larger area reduces memory density.
Innovation Solution
A semiconductor structure is designed with connecting pads that connect multiple transistors to a single MTJ, maintaining memory density by sharing transistors across MTJs through a stair-shaped pad configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory cell designs are used, then manufacturing processes are simpler, but manufacturing precision deteriorates due to misalignment sensitivity
Solution Approach 1:
The patent applies asymmetry by designing the first and second dummy word lines with different configurations relative to the memory cell. The first dummy word line extends in a first direction from the memory cell, while the second dummy word line extends in a second direction (different from the first direction) from the memory cell. This asymmetric arrangement creates different stress conditions that compensate for manufacturing misalignments, thereby improving manufacturing precision without requiring perfect alignment.
2Manufacturing precision
If dummy word lines are added to compensate for misalignment, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by adding dummy word lines only in specific locations where misalignment compensation is needed, rather than uniformly across the entire device. The first dummy word line is positioned adjacent to the memory cell extending in a first direction, and the second dummy word line is positioned adjacent to the memory cell extending in a second direction. This localized approach provides targeted misalignment compensation while minimizing overall device complexity.
3Productivity
If memory cell size is reduced to increase density, then productivity improves, but manufacturing precision deteriorates due to increased misalignment impact
Solution Approach 1:
The patent applies preliminary action by pre-configuring dummy word lines around memory cells before actual operation. These dummy word lines are designed with specific orientations (first direction and second direction) to proactively compensate for misalignment issues that would affect smaller feature sizes. By having these compensatory structures in place beforehand, the memory array can achieve higher density with reduced feature sizes while maintaining manufacturing precision through the stress-balancing effect of the asymmetric dummy word line configuration.
Data Source
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AI summary
Provided is a semiconductor structure, a memory cell and a memory array. An nT-MRAM can be realized by a relatively simple structure. Transistors connected to multiple MTJs are connected by connecting pads, thereby realizing the purpose of driving one same MTJ by n transistors without reducing the memory density.