MRAM Cell Layout with Shared Source Transistors
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Solution Overview
Problem
Spin injection type MRAM devices have a large writing current requirement, leading to an inability to reduce the area of memory cells, which limits their capacity and efficiency.
Innovation Solution
A magnetic random access memory device configuration featuring a magnetoresistive effect element with a unique layout of gate electrodes, bit lines, and bit line contacts on a semiconductor substrate, allowing for reduced memory cell area by optimizing current flow and eliminating the need for element isolation insulating films, thereby minimizing the area required for each memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spin injection type MRAM uses a conventional memory cell configuration with one cell transistor and one MTJ element, then the device can store data using TMR effect, but the writing current becomes large and the memory cell area cannot be reduced
Solution Approach 1:
The patent divides the memory cell into multiple transistors (first and second cell transistors) that share a common source region, rather than using a single transistor per MTJ element. This segmentation allows the writing current to be distributed and controlled more efficiently, reducing the current density requirements and enabling smaller cell areas while maintaining reliable data storage through the TMR effect
Solution Approach 2:
The patent merges the source regions of multiple transistors into a shared common source region. By combining the source regions of the first and second cell transistors, the design reduces redundant structures and minimizes the overall memory cell area, while the shared source region enables efficient current control for writing operations
2Productivity
If the memory cell area is reduced to increase memory capacity, then more cells can be packed, but the writing current density increases making it difficult to maintain reliable writing operation
Solution Approach 1:
The patent employs dynamic control of the writing current through multiple transistors that can be independently activated. By selectively turning on the first and second cell transistors based on the desired write operation, the design optimizes current flow paths and maintains adequate current density for reliable writing even as cell area decreases and capacity increases
3Reliability
If conventional element isolation insulating films are used to separate memory cells, then cell isolation is achieved, but the memory cell area increases
Solution Approach 1:
The patent extracts or removes the conventional element isolation insulating films from the memory cell structure. By eliminating these isolation films and relying on the inherent isolation provided by the shared source region configuration and transistor layout, the design achieves adequate cell isolation without the area penalty of additional insulating structures
Solution Approach 2:
The shared source region serves multiple functions: it acts as the source for both the first and second cell transistors, provides natural electrical isolation between adjacent memory cells, and eliminates the need for separate isolation structures. This multi-functionality achieves cell isolation without increasing area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the formation of memory cells with a smaller area, enhancing memory capacity and reducing power consumption and operation time by optimizing current flow and eliminating the need for element isolation insulating films.
Implementation Method 1
a magnetoresistive effect element formed on the active area and storing data by a change in resistance value
Data Source
AI summary
An aspect of the present disclosure, there is provided a magnetoresistive random access memory device, including, an active area formed on a semiconductor substrate in a first direction, a magnetoresistive effect element formed on the active area and storing data by a change in resistance value, a gate electrode of a cell transistor formed on each side of the magnetoresistive effect element on the active area in a second direction, a bit line contact formed on the active area and arranged alternately with the magnetoresistive effect element, a first bit line connected to the magnetoresistive effect, and a second bit line connected to the bit line contact.