MRAM Shield Line and Clamp Transistor Noise Suppression

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The spin-transfer torque writing method in magnetoresistive random access memory (MRAM) faces challenges with magnetization switching current being smaller as magnetic substance size decreases, limiting high integration, low power consumption, and high performance.

Innovation Solution

The MRAM device incorporates a memory cell array with magnetic tunnel junction (MTJ) elements using a spin-transfer torque writing method, where a sense amplifier compares cell and reference currents, and clamp transistors are used to manage these currents, with specific interconnect layer configurations to suppress noise and maintain read margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If magnetic substance size is decreased to achieve higher integration, then integration density is improved, but magnetization switching current becomes smaller which limits performance

Engineering Contradiction:
Improveintegration densityVSAvoidmagnetization switching current
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the material composition parameters of the magnetic tunnel junction by using a reference layer made of CoFeB alloy instead of conventional materials, and by optimizing the thickness parameters of various layers (CoFeB reference layer: 3-6nm, MgO barrier layer: 1-3nm, CoFeB pivot layer: 3-6nm) to achieve stable magnetization switching at reduced current levels in miniaturized devices

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If sense amplifier is used to read data from memory cell, then data reading accuracy is improved, but noise interference increases which affects read margin

Engineering Contradiction:
Improvedata reading accuracyVSAvoidnoise interference
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a shield line as an intermediary element positioned between the bit line and word line to act as a noise barrier, and adds a noise margin compensation circuit that includes a variable resistor and capacitor to dynamically compensate for noise interference and maintain adequate read margin in high-density memory devices

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary anti-action by pre-positioning the shield line to block noise before it reaches the sense amplifier, and by pre-configuring the noise margin compensation circuit with variable components that can be adjusted to counteract expected noise levels, thereby preventing noise from degrading read accuracy

Inventive Principle:
Principle #9Preliminary anti-action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances data reading accuracy and maintains performance by minimizing noise interference and ensuring correct data sensing, even in high-density memory devices.

Implementation Method 1

The MRAM is a memory device using magnetoresistive elements having a magnetoresistive effect in memory cells that store information

Methodology Applied
Scientific EffectMagnetoresistive effect: Magnetoresistance

Implementation Method 2

As a writing method of the MRAM, there is a spin-transfer torque writing method. Since this spin-transfer torque writing method has the property that the spin-transfer torque current for magnetization switching becomes smaller as a magnetic substance decreases in its size

Methodology Applied
Scientific EffectSpin-transfer torque:

Data Source

PatentUS9824736B1Memory device
Publication Date: 2017.11.21 KIOXIA CORP
  • US9824736B1 patent drawing
  • US9824736B1 patent drawing
  • US9824736B1 patent drawing

AI summary

According to one embodiment, a memory device includes a memory cell array; a generation circuit generating a reference current; a sense amplifier comparing a cell current flowing through a memory cell with the reference current; a first clamp transistor connected between the sense amplifier and the memory cell; a second clamp transistor connected between the sense amplifier and the generation circuit; a first interconnect layer connected to a gate of the first clamp transistor; a second interconnect layer connected to a gate of the second clamp transistor and arranged adjacent to the first interconnect layer; and a first shield line arranged adjacent to one of the first interconnect layer and the second interconnect layer, a fixed voltage being applied to the first shield line.