MRAM Short Detection and Data Inversion for Bit Cell Errors
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Solution Overview
Problem
Magnetic random access memory (MRAM) devices experience higher bit error rates due to dielectric breakdown of magnetic tunnel junctions, limiting their endurance and lifetime, and existing error correction circuits struggle to correct errors introduced by shorted bit cells.
Innovation Solution
Incorporating a short detection circuit and error correction mechanisms, such as majority detection and inversion schemes, to identify and correct errors in MRAM devices, allowing for data inversion to match the fixed state of shorted bit cells and reduce the number of bits that need to be switched, thereby extending the device's usable lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If magnetic tunnel junctions are used to store data in MRAM devices, then data storage capability is achieved, but dielectric breakdown occurs leading to higher bit error rates and reduced device lifetime
Solution Approach 1:
The patent inverts the data storage approach by detecting shorted bit cells and inverting the stored data states. When a shorted bit cell is detected (fixed in low resistance state), the system inverts the logical interpretation of stored values (0 becomes 1, 1 becomes 0) for that specific cell. This allows the device to continue operating correctly despite dielectric breakdown, effectively reversing the harmful effect of shorting into a manageable condition.
Solution Approach 2:
The patent converts the harmful dielectric breakdown effect into a detectable and manageable condition. By monitoring resistance states and identifying shorted cells, the system transforms the random error source into a known, correctable condition through inversion bits and error correction codes, thereby extending device lifetime despite the presence of breakdown events.
2Reliability
If error correction circuits are used to correct errors in shorted bit cells, then bit error rate is reduced, but the circuits cannot correct multiple errors within the same ECC word
Solution Approach 1:
The patent segments the error correction approach by applying inversion at the bit cell level before ECC processing. Each shorted bit cell is individually identified and its data inverted, creating a pre-corrected state that reduces the error burden on the ECC circuit. This segmentation allows the ECC circuit to focus on correcting remaining random errors rather than handling multiple systematic errors from shorted cells.
Solution Approach 2:
The patent performs preliminary error correction by detecting and inverting data in shorted bit cells before the data reaches the ECC correction stage. This preliminary action reduces the number of errors that the ECC circuit must handle, enabling it to effectively correct multiple errors within the same ECC word that would otherwise be beyond its capability.
3Reliability
If data is stored in inverted states to match shorted bit cell fixed states, then the number of errors is reduced, but additional circuit complexity is introduced for detection and inversion
Solution Approach 1:
The patent introduces inversion bits as intermediary elements between the data storage and readout paths. These inversion bits act as mediators that control whether data should be inverted based on the detected state of shorted bit cells. This intermediary mechanism allows the system to dynamically adjust data interpretation without requiring fundamental changes to the core storage architecture, thereby limiting the increase in overall circuit complexity.
Data Source
AI summary
In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.