MRAM Sidewall Protection for BEOL Interconnect Short Prevention
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Solution Overview
Problem
During the interconnect process in semiconductor Back-End-Of-Line (BEOL) memories, such as MRAM, electrical shorts can occur between the top and bottom electrodes due to the exposure of sidewalls during via etching, leading to device failure, especially as feature sizes are scaled down and there is no margin for the bit line to land on the top electrode.
Innovation Solution
Depositing one or more protection layers on the sidewalls of the memory device before via etching to prevent electrical shorts, with the first embodiment using a single layer resistant to dielectric etchants and the second embodiment employing a dual-layer protection system where the first layer is oxygen-free and the second layer resists etch-stop dielectric etchants, allowing conventional interconnect processes to proceed without shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If feature size is scaled down to minimize cell area, then device integration density is improved, but the risk of electrical shorts during via etching increases
Solution Approach 1:
A sidewall protection layer is deposited on the sidewalls of the memory element before the via etch process. This preliminary protective action ensures that even if the via etch penetrates deeper than intended and reaches the bottom electrode, the sidewall protection layer prevents direct contact and electrical shorting between the top and bottom electrodes.
Solution Approach 2:
The sidewall protection layer acts as an intermediary barrier between the via etch process and the memory element sidewalls. This intermediate layer is resistant to the via etch chemistry, providing a protective interface that prevents the etchant from damaging the underlying structures and causing shorts.
2Reliability
If via etch depth is increased to ensure connection, then interconnect reliability is improved, but the risk of exposing sidewalls and causing shorts increases
Solution Approach 1:
The sidewall protection layer is applied before the via etch process, providing preemptive protection against over-etching. This allows the via etch to proceed to the required depth for reliable interconnect connection without risking sidewall exposure, as the protection layer serves as a sacrificial or resistant barrier.
Solution Approach 2:
The sidewall protection layer provides a cushioning effect against the via etch process. Even if the etch depth varies or exceeds the intended target, the protection layer absorbs the excess etching action, preventing direct exposure of the memory element sidewalls and bottom electrode.
3Manufacturing precision
If sidewall protection layer material is selected to resist via etch, then etch resistance is improved, but the material selection and process complexity increase
Solution Approach 1:
The sidewall protection layer uses a material with different etch resistance parameters compared to the surrounding dielectric layers. By selecting materials such as silicon nitride, silicon oxide, or borazinic film that exhibit selective etch resistance to the via etch chemistry, the structure achieves the desired protection without requiring fundamentally new materials or processes.
Solution Approach 2:
The patent employs composite material structures where the sidewall protection layer is integrated with existing dielectric layers. The protection layer material is chosen to be compatible with standard semiconductor fabrication processes, allowing it to be deposited using conventional techniques alongside other process layers, thereby minimizing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protection layers effectively prevent electrical shorts between the top and bottom electrodes, enabling higher yields even with variations in etching depth, by ensuring the sidewalls are insulated during the interconnect process, thus maintaining device functionality.
Implementation Method 1
The material for the protection sleeve layer is selected to resist the etchant used to remove the dielectric material from the via in the subsequent interconnect process
Implementation Method 2
one or more protection layers deposited on the sidewall of the memory device
Implementation Method 3
The process for forming the film uses a carrier gas and a raw material gas
Data Source
AI summary
BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.