MRAM Sidewall Protection for BEOL Via Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
During the BEOL process for semiconductor memory devices like MRAM, electrical shorts can occur between the top and bottom electrodes due to the exposure of sidewalls during via etching, leading to device failure, especially as feature sizes are scaled down and there is no margin for the bit line to land on the top electrode.
Innovation Solution
Depositing one or more protection layers on the sidewalls of the memory device before interconnect via etching to prevent electrical shorts, using materials that resist etchants and etch-stop dielectric materials to ensure the top electrode remains exposed and protected, with options for single-layer or dual-layer sidewall protection sleeves and etch stop layers to address thickness variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the minimum feature size is scaled down to minimize cell area, then the device density is improved, but the margin for bit line landing on top electrode is reduced, causing sidewall exposure during via etching
Solution Approach 1:
A protection layer is deposited on the sidewalls of the memory element before the via etching process. This preliminary protective measure ensures that even if the via etch depth varies or exceeds the intended depth, the sidewalls remain protected and prevent electrical shorts, thereby resolving the manufacturing precision issue while maintaining scaled-down dimensions
Solution Approach 2:
The protection layer acts as an intermediary between the via etching process and the memory element sidewalls. This intermediate layer absorbs the harmful effect of over-etching and prevents direct contact between the etchant and the sidewalls, allowing precise control of via depth even when minimum feature sizes are reduced
2Reliability
If the via etch depth is increased to ensure top electrode exposure, then the interconnect reliability is improved, but the risk of exposing bottom electrode and causing electrical short is increased
Solution Approach 1:
The protection layer is applied beforehand to cushion against the harmful effects of deep via etching. This protective cushion allows the via etch to proceed to the required depth for reliable top electrode exposure without risking exposure of the bottom electrode, as the protection layer absorbs any excess etching and prevents direct contact between conductive materials
Solution Approach 2:
The protection layer serves as an intermediary barrier that decouples the via etching depth from the actual exposure of the bottom electrode. Even when the via etch penetrates deeply to ensure top electrode access, the protection layer remains in place to prevent electrical shorts, thereby enabling high interconnect reliability without increasing short-circuit risk
3Productivity
If the etching selectivity is reduced to speed up the via etching process, then the productivity is improved, but the control over etching depth is reduced, causing sidewall exposure
Solution Approach 1:
The protection layer is deposited in advance to provide a buffer against poor etching depth control. This allows the use of higher etching speeds with reduced selectivity, as the protection layer compensates for the increased variability in etch depth, ensuring that sidewalls are never exposed even when precision is compromised
Solution Approach 2:
The potential harm of reduced etching selectivity and poor depth control is converted into a benefit by the presence of the protection layer. The protection layer transforms what would be a destructive over-etch into a harmless process, allowing faster etching rates to be used without sacrificing sidewall integrity, thereby improving productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents electrical shorts and allows for higher yields in the fabrication of MRAM and other BEOL memories by ensuring reliable exposure of the top electrode during interconnect processing, even with variations in etching depth, thereby maintaining device functionality.
Implementation Method 1
using materials that resist etchants and etch-stop dielectric materials
Implementation Method 2
one or more protection layers deposited on the sidewall of the memory device
Data Source
AI summary
BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching. In either the first or second embodiments a single layer or a dual layer etch stop layer structure can be deposited over the wafer after the sidewall protection sleeve has been formed and before the inter-layer dielectric (ILD) is deposited.