MRAM Memory Circuit Single Mask Patterning for Reduced Fabrication Steps
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Solution Overview
Problem
The existing MRAM circuit fabrication processes require multiple masking and etching steps, which are time-consuming and costly, and the direct contact between bottom electrodes and metallization layers in some embodiments limits the writing operation capability to read-only functionality due to interference effects between adjacent magnetic bits.
Innovation Solution
The proposed solution involves patterning a magnetic tunnel junction (MTJ) stack through a single mask to define fully or partially isolated individual stacks, eliminating the need for multiple etching steps and allowing direct contact between metallization layers and conducting lines, thereby reducing processing time and cost while enabling read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masking and etching steps are used to fabricate MRAM circuits, then manufacturing precision and isolation of magnetic storage elements are improved, but processing time and cost increase significantly
Solution Approach 1:
The patent combines multiple masking and etching steps into a single integrated process. Specifically, a first mask layer is formed over the substrate, and a first etch process simultaneously defines both the bit line openings and the magnetic storage element structures, eliminating the need for separate masking steps for each feature.
Solution Approach 2:
The single mask layer serves multiple functions: it defines the bit line openings, defines the magnetic storage element footprints, and provides etch stopping protection. This multi-functional mask approach replaces what would traditionally require multiple specialized mask layers for different purposes.
2Manufacturing precision
If multiple masking and etching steps are used to fabricate MRAM circuits, then manufacturing precision and isolation of magnetic storage elements are improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple masking and etching steps into a single integrated process. Specifically, a first mask layer is formed over the substrate, and a first etch process simultaneously defines both the bit line openings and the magnetic storage element structures, eliminating the need for separate masking steps for each feature.
Solution Approach 2:
The single mask layer serves multiple functions: it defines the bit line openings, defines the magnetic storage element footprints, and provides etch stopping protection. This multi-functional mask approach replaces what would traditionally require multiple specialized mask layers for different purposes.
3Device complexity
If direct contact between bottom electrodes and metallization layers is implemented, then device complexity is reduced, but writing operation capability is lost due to interference effects
Solution Approach 1:
The patent introduces a non-magnetic barrier layer as an intermediary between the bottom electrode and the metallization layer. This barrier layer prevents direct magnetic field interference between adjacent bit cells during write operations, while still allowing electrical contact to be established through the barrier layer.
Solution Approach 2:
The patent segments the magnetic storage elements with spacing between adjacent stacks, and introduces barrier layers at critical interfaces. This segmentation isolates the magnetic fields of adjacent bits, preventing interference during write operations while maintaining the simplified direct-contact architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces processing steps and costs, enhancing yield and allowing for read operations, although it may compromise writing capability due to interference effects, making it suitable for low-cost, disposable, or read-only memory applications.
Implementation Method 1
Magnetic (or magneto-resistive) random access memory (MRAM) circuits
Implementation Method 2
The write word line 118c for the writing operation in a bit tell has no contact with the bottom electrode 112, and when energized, induces a magnetic field at a junction of the MTJ stack 122
Data Source
AI summary
Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.