MRAM Slot Via Bit Line Layout for Lower Series Resistance
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Solution Overview
Problem
The scaling down of MRAM cells is limited by resolution limits of lithography and etching techniques, leading to increased series resistance and higher power consumption.
Innovation Solution
The integration of slot vias in the bit lines of MRAM cells, fabricated using the same process as logic region vias, reduces series resistance by contacting a column of MRAM cells, thereby improving manufacturing efficiency and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MRAM cells are scaled down to increase functional density, then production efficiency and cost are improved, but series resistance increases leading to higher power consumption
Solution Approach 1:
The patent introduces slot vias that extend horizontally across multiple MRAM cell columns rather than vertically through a single column. This dimensional change from vertical to horizontal via configuration allows a single via to contact multiple cell columns, reducing the number of vias needed and decreasing total series resistance in the bit line while maintaining high functional density
Solution Approach 2:
The slot via structure merges multiple via functions into a single continuous conductive element that spans across multiple MRAM cell columns. This consolidation reduces the total number of via interfaces and contact resistance points, thereby lowering series resistance and power consumption while supporting scaled-down cell dimensions
2Quantity of substance
If MRAM cells are scaled down using existing lithography and etching techniques, then device density is improved, but manufacturing complexity increases due to resolution limits
Solution Approach 1:
The slot via formation process is designed to be compatible with existing logic region via fabrication processes. By using the same lithography and etching tools and procedures for both logic and memory regions, the patent achieves multi-functionality of the manufacturing equipment, reducing manufacturing complexity while enabling higher device density through continued scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of slot vias in MRAM bit lines effectively decreases series resistance and power consumption, enhancing the performance and efficiency of MRAM devices.
Implementation Method 1
An MRAM cell is formed by a magnetic tunneling junction (MTJ) comprising two ferromagnetic layers which are separated by a thin insulating barrier, and operates by tunneling of electrons between the two ferromagnetic layers through the insulating barrier
Data Source
AI summary
A semiconductor structure includes a third metal layer immediately above a second metal layer that is over a first metal layer. The second metal layer includes magnetic tunneling junction (MTJ) devices in a memory region and a first conductive feature in a logic region. Each MTJ device includes a bottom electrode and an MTJ stack over the bottom electrode. The third metal layer includes a first via electrically connecting to the first conductive feature, and a slot via over and electrically connecting to the MTJ stack of the MTJ devices. The slot via occupies space extending continuously and laterally from a first one to a last one of the MTJ devices. The first via is as thin as or thinner than the slot via. The third metal layer further includes second and third conductive features electrically connecting to the first via and the slot via, respectively.