MRAM Spacer Protects Resistance Switching Element
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Solution Overview
Problem
In the fabrication of integrated circuits with magnetoresistive random access memory (MRAM) arrays, the topography of the wafer causes height differences between memory cells, leading to exposure of resistance switching elements during etching back processes, which results in unwanted electrical connections and potential damage.
Innovation Solution
The use of spacers with higher etch resistance properties than the dielectric layer ensures that resistance switching elements remain protected during etching back, preventing exposure and subsequent electrical connections, by selectively etching the dielectric layer while maintaining the spacer coverage over the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching back process is performed to remove dielectric layer, then planarization is achieved, but resistance switching elements are exposed and damaged
Solution Approach 1:
A spacer layer is formed over the resistance switching element before the etching back process. This preliminary protective layer remains during etching to prevent exposure of the resistance switching element, and is removed only after the etching back is complete, thus protecting the element while achieving planarization.
Solution Approach 2:
The spacer layer acts as an intermediary protective barrier between the etchant and the resistance switching element. It allows the etching back process to proceed while mediating the harmful effect of the etchant on the resistance switching element, preventing direct contact and damage.
2Reliability
If spacer layer is used to protect resistance switching element, then element integrity is maintained, but process complexity increases
Solution Approach 1:
The spacer layer serves multiple functions: it protects the resistance switching element during etching back, defines the boundary for dielectric layer removal, and can serve as a mask for subsequent processing steps. This multi-functionality reduces the need for additional separate protective layers or process steps.
Solution Approach 2:
The spacer layer is formed with uniform material composition and thickness across the wafer, providing consistent protection for all resistance switching elements. This homogeneity simplifies the etching process by ensuring uniform etch rates and consistent protection, reducing the need for complex process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents damage to the resistance switching elements and avoids unwanted electrical connections from subsequently deposited conductive materials, maintaining the integrity and functionality of the memory cells despite wafer topography-induced height differences.
Implementation Method 1
The spacer is made of a first material and the dielectric layer is made of a second material, wherein the first material has a higher etch resistance property than the second material
Data Source
AI summary
A memory device includes a bottom electrode, a resistance switching element, a top electrode, a spacer and a conductive feature. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching electrode. The spacer abuts the resistance switching element. The conductive feature is over the top electrode. The spacer is at least partially between the conductive feature and the top electrode.