MRAM Bit Fabrication via Spacer Layer Protection
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Solution Overview
Problem
Current manufacturing yields of magnetoresistive random access memory (MRAM) devices are low due to corrosion issues in etching processes during the fabrication of magnetic tunneling junction (MTJ) layers, which hinders the reduction in device size as demanded by the industry.
Innovation Solution
A method involving a stack of layers with a conductive hardmask, top and bottom electrode layers, and a tunneling barrier layer is introduced into a processing chamber, where the top electrode and tunneling barrier layers are etched using a halogen-free process, followed by deposition of a spacer layer to prevent redeposition of byproducts, and a subsequent etching process that maintains vertical sidewalls without halogen-based plasma, simplifying the processing and increasing yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional etching processes are used to fabricate MRAM bits, then the etching process can remove material, but the MTJ layers are corroded during etching
Solution Approach 1:
A spacer layer is deposited over the MTJ layers before the etching process. This spacer layer acts as an intermediary protective barrier that prevents direct contact between the etching plasma and the MTJ layers, thereby preventing corrosion while still allowing the etching process to proceed. The spacer layer is selectively removed later to expose the patterned MTJ structure.
Solution Approach 2:
The spacer layer is deposited in advance of the etching process to preemptively protect the MTJ layers from corrosion. This preliminary protective action occurs before the harmful etching process begins, ensuring the MTJ layers are shielded from plasma exposure that would otherwise cause corrosion.
2Area of moving object
If device size is reduced to meet industry demands, then integration density increases, but manufacturing yields decrease due to corrosion issues
Solution Approach 1:
The spacer layer serves as a protective intermediary that enables safe processing of smaller devices. By preventing corrosion during etching, the spacer layer ensures that miniaturized MRAM bits can be manufactured with high yields, overcoming the limitation that smaller device size previously caused yield degradation.
3Productivity
If halogen-based plasma is used in etching, then etching rate is improved, but corrosion of MTJ layers occurs
Solution Approach 1:
The spacer layer is deposited between the MTJ layers and the etching plasma environment. This intermediary barrier allows the use of halogen-based plasma for efficient etching while preventing the plasma from directly corroding the MTJ layers. The spacer layer absorbs the harmful effects of the plasma chemistry.
Solution Approach 2:
The spacer layer transforms the potentially harmful halogen-based plasma into a beneficial tool. By using the spacer as a sacrificial protective layer, the process can utilize the high etching rate of halogen plasma on the spacer material itself, while the MTJ layers remain protected underneath.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents corrosion of MTJ layers, enhances manufacturing yields, and maintains high performance with achieved tunneling magnetoresistance and resistance values, demonstrating improved reliability and efficiency in MRAM bit fabrication.
Implementation Method 1
depositing a spacer layer to prevent redeposition of byproducts
Implementation Method 2
the top electrode layer and the tunneling barrier layer are etched
Data Source
AI summary
A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing.