MRAM Structure Reducing Step Height and Void Formation

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Solution Overview

Problem

Conventional MRAM structures face challenges with large step height and extreme low-k material voids between adjacent MTJs, leading to complex and costly manufacturing processes and difficulties in scaling down critical dimensions.

Innovation Solution

The MRAM structure and manufacturing method involve reducing the step height by simplifying the process through the use of a silicon carbide layer, silicon-rich oxide layer, bottom electrode via, magnetic tunneling junction, and conformable oxide layers, which extend from the array region to the logic region, along with a planarization operation to improve cycle time and reduce manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional MRAM structure is used with extreme low-k material, then dielectric properties are improved, but step height increases and manufacturing complexity increases

Engineering Contradiction:
Improvedielectric propertiesVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the extreme low-k dielectric material from the MRAM structure entirely, replacing it with conventional dielectric materials. This extraction of the problematic material eliminates the manufacturing complexity and step height issues while maintaining adequate dielectric properties through alternative design approaches.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the dielectric material parameters by substituting extreme low-k materials with conventional dielectric materials having different physical and chemical properties. This parameter change simplifies the manufacturing process while still achieving the required electrical isolation and dielectric performance.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If conventional MRAM structure with extreme low-k material is used, then dielectric properties are improved, but step height between memory array edge and logic region increases

Engineering Contradiction:
Improvedielectric propertiesVSAvoidstep height
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent extracts and removes the extreme low-k dielectric material that causes excessive step height, replacing it with conventional dielectric materials that provide adequate electrical isolation with reduced step height, thereby improving planarity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the dielectric material parameters by replacing extreme low-k materials with conventional dielectric materials, which alters the physical and chemical properties to achieve reduced step height while maintaining functional dielectric performance.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If conventional MRAM structure is used, then manufacturing process is complex, but manufacturing precision can be maintained

Engineering Contradiction:
Improvecritical dimension controlVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent removes the extreme low-k dielectric material and associated complex manufacturing steps, simplifying the overall manufacturing process while maintaining critical dimension control through conventional materials and established fabrication techniques.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the material parameters by substituting extreme low-k dielectric materials with conventional dielectric materials, which have more established processing windows and fewer manufacturing constraints, thereby reducing process complexity while maintaining precision.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If extreme low-k material is used in MRAM structure, then dielectric properties are improved, but low-k dielectric voids form between adjacent MTJs

Engineering Contradiction:
Improvedielectric propertiesVSAvoidvoid formation
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts and eliminates the extreme low-k dielectric material that is prone to forming voids during fabrication, replacing it with conventional dielectric materials that provide adequate electrical isolation without the void formation problem, thereby improving manufacturing yield.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the step height and eliminates low-k dielectric voids between MTJs, enhancing manufacturing efficiency and reducing costs while maintaining the integrity of the MRAM structure.

Implementation Method 1

The magnetization direction of free layer can be reversed by applying a current through tunnel layer, which causes the injected polarized electrons within free layer to exert so-called spin torques on the magnetization of free layer.

Methodology Applied
Scientific EffectSpin torque transfer:

Implementation Method 2

The electrons are polarized to the same magnetization direction of pinned layer after passing pinned layer; flowing through tunnel layer; and then into and accumulating in free layer.

Methodology Applied
Scientific EffectElectron polarization: Polarisation

Data Source

PatentUS10991408B2Magnetic random access memory structure and manufacturing method of the same
Publication Date: 2021.04.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10991408B2 patent drawing
  • US10991408B2 patent drawing
  • US10991408B2 patent drawing

AI summary

The present disclosure provides a method for manufacturing a magnetic random access memory (MRAM) structure, including forming a magnetic tunneling junction (MTJ) structure in a first region, forming a dielectric stack over the first region and a second region different from the first region, etching an upper portion of the dielectric stack in the first region and the second region, and performing a planarization operation over the remaining portion of the dielectric stack in the first region and the second region.