MRAM MTJ Step-Trench Fabrication for Smaller, Lower-Power Cells
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Solution Overview
Problem
Existing magnetoresistive random access memory (MRAM) devices face issues such as high chip area, high cost, high power consumption, limited sensitivity, and susceptibility to temperature variations.
Innovation Solution
A method for fabricating MRAM devices involving the formation of a magnetic tunneling junction (MTJ) with specific trench profiles, including a first trench with a wider width and a second trench with a narrower width, forming a step profile, and subsequent planarization to create a smooth surface for improved electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional MRAM fabrication methods are used, then device functionality is achieved, but chip area is large and cost is high
Solution Approach 1:
The patent divides the trench structure into multiple segments with different depths and widths (first trench, second trench, third trench) to create a stepped profile. This segmentation allows selective etching at different levels, enabling precise formation of contact holes and interlayer connections while reducing the overall chip area required for MRAM devices.
Solution Approach 2:
The patent introduces vertical dimensionality by creating trenches of different depths (first trench at first depth, second trench at second depth, third trench at third depth). This multi-level trench structure enables three-dimensional interconnect architecture that reduces planar chip area while maintaining electrical connectivity through vertical stacking of conductive layers.
2Use of energy by stationary object
If conventional MRAM structures are used, then basic storage function is provided, but power consumption is high
Solution Approach 1:
The patent modifies the physical parameters of the MTJ structure by creating precisely controlled trenches with specific depths, widths, and positions. The first trench has width W1 and depth D1, the second trench has width W2 and depth D2, and the third trench has width W3 and depth D3. These parameter changes enable optimized current paths and magnetic tunneling junction configurations that reduce power consumption while maintaining data retention reliability.
3Measurement precision
If conventional MRAM devices are used, then storage capability is achieved, but sensitivity is limited and temperature stability is poor
Solution Approach 1:
The patent applies local quality by creating region-specific trench structures with different dimensions and depths at different locations within the device. The first, second, and third trenches are positioned at specific locations to locally optimize magnetic field detection sensitivity and provide localized thermal management that reduces temperature variation effects on device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces chip area, lowers power consumption, enhances sensitivity, and stabilizes performance against temperature variations, resulting in an improved MRAM device.
Implementation Method 1
The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices
Data Source
AI summary
A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a dielectric layer on the MTJ, performing a first etching process to form a first trench in the dielectric layer, and performing a second etching process to form a second trench in the dielectric layer. Preferably, a bottom surface of the second trench is lower than a bottom surface of the first trench, a width of the second trench is less than a width of the first trench, and the first trench and the second trench together form a step profile.