MRAM Storage Array Interconnection Structure for High Density
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Solution Overview
Problem
Conventional MRAM storage devices with a double finger 1T1R structure face a technical challenge in achieving high storage unit density due to the increased unit area of transistors required for a large power supply capability.
Innovation Solution
The proposed storage array and interconnection structure utilize a unique configuration where storage units in odd-numbered and even-numbered columns are connected to bit lines and source lines in a specific alternating pattern, allowing for the multiplexing of transistors and reducing the area required for each storage unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a double finger 1T1R structure is used to provide large power supply capability, then the power supply capability is improved, but the unit area of the transistor is increased
Solution Approach 1:
The transistor is divided into two fingers (first finger and second finger), each capable of independently conducting current. This segmentation allows the total current capacity to be distributed across multiple smaller conduction paths, maintaining power supply capability while reducing the area required for each individual conduction path.
Solution Approach 2:
The first and second fingers of the transistor serve multiple functions: they can independently conduct current during read operations, and can be selectively controlled during write operations. This multi-functionality allows the same transistor structure to handle both read and write operations efficiently, maintaining power capability without increasing area.
2Power
If the unit area of transistor is increased to provide large power supply capability, then the power supply capability is improved, but the storage unit density is limited
Solution Approach 1:
By segmenting the transistor into two fingers, the effective conduction area is divided into smaller units that can be more efficiently packed. This allows multiple storage units to be arranged in closer proximity while each transistor still maintains sufficient power supply capability through the combined capacity of its fingers.
Solution Approach 2:
The first and second fingers are merged into a single transistor structure that shares common control gates and control lines. This merging reduces the total area required compared to using two separate transistors, while the combined finger structure maintains the necessary power supply capability for reliable operation.
3Power
If a double finger 1T1R structure is used, then the power supply capability is improved, but the area required for each storage unit is increased
Solution Approach 1:
The storage unit area is segmented into regions controlled by different word lines (first and second word lines), allowing independent control of each segment. This segmentation enables more efficient use of the total area by activating only the necessary segments during operations, reducing the effective area required per storage unit while maintaining power capability.
Solution Approach 2:
The patent utilizes a three-dimensional arrangement where bit lines, source lines, and word lines are positioned at different vertical levels. This dimensional arrangement allows for more compact packing of storage units by utilizing vertical space, thereby reducing the planar area required for each storage unit while maintaining adequate power supply capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases the storage unit density while maintaining the power supply capacity of the transistors, thereby addressing the limitations of existing arrays with double finger structures.
Implementation Method 1
Magnetoresistive Random Access Memory (MRAM) is a memory of which storage units store information using magnetic states
Implementation Method 2
By a certain MRAM, a nonvolatile memory can be stored and units can be written multiple times during the service life of the memory. In order to realize the switch of high and low resistance states of an MRAM, a 1T1R structure is generally formed by a storage unit and a transistor, and by changing the current direction of the transistor, the storage unit can be written into a low resistance state or a high resistance state
Data Source
AI summary
The present disclosure provides a storage array, and an interconnection structure and a method for operating thereof. The storage array includes: storage units and transistors located in each column and each row, each transistor having a first source/drain and a second source/drain; wherein, a storage unit in an odd-numbered column connected to a first bit line and a second source line; the first source/drain of a transistor in an odd-numbered column is connected to a first source line; the second source/drain of a transistor in an odd-numbered column is connected to a second source line; a storage unit in an even-numbered column connected to a second bit line and a first source line; the first source/drain of a transistor in an even-numbered column is connected to a second source line; and the second source/drain of a transistor in an even-numbered column is connected to a first source line.