MRAM Top Contact Formation via Etch-Back Planarization
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Solution Overview
Problem
Scaling down MRAM devices to smaller nodes poses challenges in making electrical contacts to the top electrode of magnetic tunnel junctions due to reduced vertical height and critical dimension, with existing techniques like CMP and special vias being unsuitable for advanced process nodes like 28 nm.
Innovation Solution
The method involves forming a magnetic tunnel junction between dielectric layers, using a metal hard mask and a conductive layer directly on the top contact, with additional dielectric layers and metal fills to ensure proper planarization and connection, employing processes like CMP and dual damascene for efficient top contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MRAM device size is scaled down to increase density, then device density is improved, but making electrical contact to the top electrode becomes increasingly difficult
Solution Approach 1:
The patent transitions from planar contact formation to three-dimensional contact formation by etching vias through dielectric layers to reach the top electrode. This vertical dimension approach allows electrical contact to be made to scaled-down MTJ devices by creating conductive pathways through the depth of the structure, overcoming the limitations of horizontal scaling.
Solution Approach 2:
The patent introduces an intermediary via structure that bridges the gap between the interconnect layer and the top electrode. This via acts as a mediator, allowing electrical connection to be established through the dielectric layers without requiring direct access to the top electrode surface, thus solving the contact formation problem in scaled devices.
2Ease of operation
If conventional CMP process is used for planarization, then top electrode exposure is achieved, but MTJ metal hard mask height is limited by CMP tolerance which degrades yield
Solution Approach 1:
The patent extracts the planarization function from the CMP process by using etch-back to remove excess dielectric material. This separates the dielectric removal step from the metal hard mask formation, allowing the metal hard mask height to be determined by deposition control rather than CMP tolerance, thereby improving manufacturing precision.
Solution Approach 2:
The patent replaces the mechanical CMP process with a chemical etching process for planarization. This substitution eliminates the mechanical contact and associated tolerance issues of CMP, allowing for more precise control of the dielectric layer thickness and better preservation of the metal hard mask dimensions.
3Reliability
If special vias or back-end-of-line interconnect landing is used for top contact formation, then electrical connectivity is achieved, but these techniques are not practical for advanced process nodes of 40 nm or below
Solution Approach 1:
The patent creates a universal via formation process that can be applied across multiple process nodes from 40 nm down to 28 nm and below. The standard via etching and filling approach serves multiple functions: creating electrical contact, defining contact geometry, and integrating with the overall device fabrication flow, making it adaptable to various advanced process nodes.
Solution Approach 2:
The patent adjusts via dimensions, etch selectivity ratios, and filling parameters to optimize contact formation for different process nodes. By changing these process parameters rather than the fundamental approach, the same via-based contact formation technique remains effective across scaling generations from 40 nm to 28 nm and below.
Data Source
AI summary
A magnetoresistive random access memory (MRAM) device includes a top electrode or top contact above a metal hard mask which has a limited height due to process limitations in advanced nodes. The metal hard mask is provided on a magnetic tunnel junction (MTJ). The top contact for the MTJ is formed within a dielectric layer, such as a low dielectric constant (low-k) or extremely low-k layer. An additional dielectric layer is provided above the top contact for additional connections for additional circuitry to form a three-dimensional integrated circuit (3D IC).