MRAM MTJ Top Electrode Via Planarization for Low Resistance
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Solution Overview
Problem
Conventional MRAM cell fabrication methods result in a V-shaped recess at the top electrode via, leading to increased resistance due to oxidation, dielectric formation, and voids, which affect the integrity and performance of the memory device.
Innovation Solution
A chemical-mechanical planarization process is employed to form a top electrode via with a flat surface, eliminating the V-shaped recess and ensuring a stable interface with the overlying conductive via, thereby reducing resistance and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional MRAM cell fabrication methods are used, then the manufacturing process is simple, but a V-shaped recess is formed at the top electrode via leading to increased resistance and defects
Solution Approach 1:
The patent applies chemical-mechanical planarization (CMP) to change the surface morphology parameter of the top electrode via from V-shaped to flat. This process modifies the physical state and surface characteristics of the conductive material, achieving a flat surface that eliminates oxidation and void formation while maintaining manufacturing feasibility
Solution Approach 2:
The patent replaces conventional mechanical etching methods with chemical-mechanical planarization. Instead of relying solely on mechanical removal to define the via shape, the process uses chemical reactions combined with mechanical polishing to achieve the desired flat surface, thereby eliminating the V-shaped recess and associated defects
2Reliability
If conventional fabrication methods are used, then the process is straightforward, but oxidation and dielectric formation occur in the V-shaped recess increasing resistance
Solution Approach 1:
The patent applies preliminary anti-action by performing chemical-mechanical planarization immediately after via formation to eliminate the V-shaped recess before oxidation can occur. By addressing the geometric defect beforehand, the process prevents subsequent harmful oxidation and dielectric formation that would increase resistance and degrade electrical connectivity
Solution Approach 2:
The patent converts the potentially harmful V-shaped geometry into a beneficial flat surface through chemical-mechanical planarization. The process transforms the structural disadvantage (V-shape) into an advantage (flat surface), eliminating oxidation sites and improving electrical connectivity while maintaining the via's conductive function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The flat surface of the top electrode via enhances the electrical connectivity and reliability of the MRAM cell by preventing oxidation and void formation, ensuring low resistance and improved device performance.
Implementation Method 1
A chemical-mechanical planarization process is employed to form a top electrode via with a flat surface
Implementation Method 2
preventing oxidation and void formation, ensuring low resistance and improved device performance
Data Source
AI summary
Some embodiments relate to a semiconductor structure having a magnetic tunnel junction (MTJ) on a substrate and a top electrode on the MTJ. A first segment of a top surface of the top electrode adjacent to a first sidewall of the top electrode is different from a second segment of the top surface of the top electrode adjacent to a second sidewall of the top electrode. A sidewall spacer comprises a first spacer on the first sidewall of the top electrode and a second spacer on the second sidewall of the top electrode. A first surface of the first spacer comprises a first curve and a second surface of the second spacer comprises a second curve. A dielectric layer is around the MTJ and top electrode.