MRAM Cell Integration Using Transparent Dielectric Alignment
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Solution Overview
Problem
Magnetic random access memory (MRAM) devices face challenges in aligning patterned MTJ stack layers with underlying interconnect structures due to non-transparent metal layers, leading to potential inoperability and requiring complex, costly processes for integrating MRAM cells at lower interconnect levels within integrated circuits.
Innovation Solution
A method for forming MRAM cells with a magnetic tunnel junction (MTJ) element between the pre-metal dielectric (PMD) or CA level and the first metal line (M1) level, using a simplified process that reduces the number of masks needed, allowing for integration with logic devices in a cost-effective and reliable manner, and utilizing extreme ultra-violet (EUV) lithography for precise patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MTJ stack layers are patterned using conventional lithography and etch techniques, then the metal layers provide structural integrity, but the non-transparent metal layers prevent proper alignment with underlying interconnect structures
Solution Approach 1:
The patent introduces alignment marks and transparent dielectric layers before patterning the MTJ stack, enabling precise alignment to be performed in advance. The alignment marks are formed on the substrate before depositing the MTJ stack layers, and transparent dielectric layers are used during patterning to allow light transmission for alignment verification, thus resolving the alignment issue before the actual stacking process begins.
Solution Approach 2:
The patent uses transparent dielectric layers as intermediary materials between the metal interconnect structures and the MTJ stack layers. These dielectric layers allow light to pass through during lithography alignment while providing the necessary structural support and insulation. This intermediary layer enables optical alignment techniques to work effectively despite the presence of opaque metal layers below.
2Manufacturing precision
If MRAM cells are integrated at higher interconnect levels, then alignment is easier, but portability and integration density are reduced
Solution Approach 1:
The patent performs alignment mark formation and transparent layer preparation at lower interconnect levels before integrating the MTJ stack, enabling precise alignment to be achieved even at lower levels where portability is more critical. This preliminary alignment preparation allows the same level of precision to be achieved regardless of the interconnect level at which MRAM cells are integrated.
3Manufacturing precision
If complex multi-mask processes are used for integrating MRAM components, then alignment accuracy improves, but manufacturing cost and process time increase
Solution Approach 1:
The patent forms all necessary alignment marks and transparent dielectric structures in advance, before the MTJ stack deposition. This preliminary preparation allows subsequent patterning steps to use fewer masks since the alignment references are already in place. The alignment marks are created using standard lithography processes that are already part of the manufacturing flow, avoiding the need for additional specialized masking steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable and cost-effective integration of MRAM cells with logic components at lower interconnect levels, reducing mask complexity and allowing for more compact MRAM cell formation, while maintaining compatibility with logic processing and minimizing the number of masks required.
Implementation Method 1
MRAM, for example, includes magnetic tunnel junction (MTJ) element which uses magnetic polarization to store information
Implementation Method 2
utilizing extreme ultra-violet (EUV) lithography for precise patterning
Data Source
AI summary
Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.