MRAM Verify Read Circuit for TDDB Failure Detection
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Solution Overview
Problem
Semiconductor storage devices face challenges in ensuring the reliability of data written in memory cells due to variations in characteristics, leading to potential false reads and write failures, especially in MRAMs with MTJ elements, which can result in Time Dependent Dielectric Breakdown failures.
Innovation Solution
The semiconductor storage device employs a self-referencing read operation that includes a verify read after writeback write, allowing for immediate detection of write failures and repeated writeback operations to ensure data reliability, while also modifying voltage and current applications to reduce stress on the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high program voltage is applied to write data in memory cells, then write speed is improved, but Time Dependent Dielectric Breakdown failures increase
Solution Approach 1:
The patent applies preliminary action by performing a verify read operation immediately after the writeback write operation to detect write failures before they propagate. This early detection mechanism allows the system to identify and correct potential TDDB failures before they manifest as permanent data loss, thereby maintaining reliability without sacrificing write speed.
Solution Approach 2:
The patent implements feedback through the verify read operation that reads back the data immediately after writing to confirm successful storage. This feedback loop provides real-time information about write operation success, enabling the system to detect and correct write failures caused by TDDB effects without requiring higher program voltages, thus resolving the contradiction between write speed and reliability.
2Reliability
If verify read operation is performed after writeback write, then data reliability is improved, but operation time increases
Solution Approach 1:
The patent merges the verify read operation with the existing read circuitry and control logic of the MRAM system. By integrating the verify function into the standard read path rather than adding separate verification hardware, the patent minimizes the time overhead while achieving enhanced data reliability through immediate post-write verification.
Solution Approach 2:
The patent maintains continuity of useful action by performing the verify read operation in immediate succession to the writeback write operation without interrupting the operational flow. This continuous verification approach ensures that the time penalty is minimized while maintaining uninterrupted data validation, resolving the contradiction between reliability improvement and time loss.
3Reliability
If repeated writeback operations are performed, then write failure detection is improved, but energy consumption increases
Solution Approach 1:
The patent applies partial action by performing the verify read operation only when necessary - specifically after writeback write operations that may be susceptible to TDDB failures. Rather than continuously verifying all write operations, the system selectively applies verification to critical paths, thereby detecting write failures without proportionally increasing energy consumption across all operations.
Data Source
AI summary
A semiconductor storage device includes a memory cell and a control circuit. In an overall read operation, the control circuit performs a first read operation to detect a first voltage and determine first data from the detected first voltage, writes second data to the memory cell, performs a second read operation to detect a second voltage and determine the second data from the detected second voltage, and compares the first data and the second data based on the first voltage and the second voltage to determine a value of the first data. When the first data and the second data are different, the control circuit performs a sequence of operations that includes a second write operation to write the first data and a verify read operation. Based on third data detected by the verify read operation, the control circuit ends the overall read operation or repeats the sequence of operations.