MRAM Write Circuit with State Transition Detection
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Solution Overview
Problem
Conventional MRAM devices continue to consume unnecessary power during write operations due to their inability to instantly detect state transitions of data cells, leading to prolonged write operations and inefficient power management.
Innovation Solution
An integrated read/write circuit with a state transition recognition circuit that compares the resistance of a target data cell to a reference cell, allowing for immediate detection and cessation of the write operation when a state transition occurs, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional MRAM devices perform write operations without instant state transition detection, then the write operation can be completed, but power is unnecessarily consumed during the entire write operation period
Solution Approach 1:
The patent implements a state transition detection circuit that continuously monitors the resistance state of the data cell during the write operation. When the circuit detects that the resistance has changed from high to low (indicating successful state transition), it generates a feedback signal to terminate the write operation immediately. This feedback mechanism eliminates unnecessary power consumption by stopping the write operation as soon as the state transition is achieved, rather than continuing for a fixed duration.
2Measurement precision
If MRAM devices use separate read and write circuits, then state transition detection can be performed, but the detection can only occur at predetermined intervals, causing delayed detection between operations
Solution Approach 1:
The patent merges the read and write circuits into a single integrated circuit that can perform both functions. The state transition detection capability is integrated into the write circuit, allowing continuous monitoring during the write operation without being limited by separate circuit operation intervals. This integration enables immediate detection of state transitions at any moment during the write operation, eliminating the timing delays inherent in separate circuit architectures.
3Reliability
If MRAM devices keep performing write operation for sufficient time to secure state transition, then state transition is guaranteed to occur, but power consumption increases and operational efficiency decreases
Solution Approach 1:
The state transition detection circuit provides real-time feedback during the write operation by monitoring resistance changes. When the feedback signal indicates that the state transition has been successfully achieved (resistance change from high to low), the write operation is immediately terminated. This ensures reliability by confirming state transition occurrence while minimizing power consumption by avoiding unnecessary continuation of the write operation.
Solution Approach 2:
The write operation itself generates the conditions for its own termination. The act of writing changes the resistance state of the data cell, and the detection circuit monitors this change to automatically stop the write operation. The system uses its own operational effects (resistance change during writing) to trigger the termination condition, eliminating the need for external timing control or continuous power supply.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the MRAM device to stop write operations instantly upon detecting state transitions, significantly reducing power consumption and improving operational efficiency.
Implementation Method 1
a state transition recognition circuit suitable for detecting a state transition of the target data cell
Implementation Method 2
The change in the polarity of the free layer 104 may change the resistance of the MTJ. For example, when the polarities are aligned to the same direction as illustrated in FIG. 1A, the MTJ may have a low resistance. When the polarities are not aligned to the same direction as illustrated in FIG. 1B, the MTJ may have a high resistance.
Data Source
AI summary
A semiconductor memory system comprising: a memory device including a plurality of data cells; a read/write circuit suitable for performing a write operation to a target data cell among the data cells; and a state transition recognition circuit suitable for detecting a state transition of the target data cell, and ending the write operation according to the detection result of the state transition of the target data cell.