Massively Reduced Instruction Set Processor for Low Latency IP Packet Processing

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Solution Overview

Problem

Embedded devices with limited resources and cost constraints struggle to handle high-bandwidth data communications, such as video delivery, due to high latency and unreliability issues with existing OS-based architectures.

Innovation Solution

A massively reduced instruction set processor (mRISP) with only two instructions (LOAD and MOVE) and specialized registers for processing IP packets, optimized for low latency and high-speed data communications, operates without an operating system to provide predictable and efficient processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a general purpose CPU with operating system is used in embedded devices, then the device can handle multiple tasks and protocols, but the processing latency increases and reliability decreases under resource constraints

Engineering Contradiction:

Improveprotocol processing capabilityVSAvoidprocessing latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the protocol processing function from the general-purpose OS environment, creating a dedicated protocol processing unit that operates independently. This segmentation allows protocol processing to occur in a controlled, deterministic environment without OS overhead, resolving the contradiction between versatility and latency by isolating the time-critical function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention extracts the protocol processing logic from the operating system kernel and application layer, implementing it as a separate hardware-accelerated function. This extraction removes the variable latency introduced by OS scheduling and context switching, while preserving the ability to handle multiple protocols through configurable processing rules.

Inventive Principle:

Principle #2Taking out (Extraction)

2Adaptability or versatility

If a general purpose CPU with operating system is used in embedded devices, then the device can run application software, but the processing reliability decreases due to deadlocks and freezes

Engineering Contradiction:

Improvesoftware execution capabilityVSAvoidsystem stability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the system into a reliable protocol processing domain and a flexible software execution domain. The protocol processing occurs in a dedicated hardware unit with deterministic behavior, while application software runs in a controlled environment with limited resources. This segmentation prevents software bugs from causing system-wide deadlocks while preserving software versatility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention introduces an intermediary layer between the OS and protocol processing functions - a dedicated hardware unit with its own control logic. This intermediary handles protocol operations directly without involving the OS kernel, preventing OS-level deadlocks from affecting protocol processing reliability while allowing the OS to continue providing software execution capabilities.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If a specialized processor is designed for low latency processing, then the processing speed increases, but the device complexity increases

Engineering Contradiction:

Improvepacket processing rateVSAvoidprocessor architecture

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent implements a universal protocol processing unit that can handle multiple communication protocols and data formats through configurable rules rather than dedicated hardware for each protocol. This multi-functionality achieves high processing speeds while controlling complexity by using a single reconfigurable engine instead of multiple specialized processors.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention achieves protocol versatility through parameter changes in the processing rules and configuration registers rather than structural changes. The same hardware unit can process different protocols by loading different rule sets and configuration parameters, maintaining low complexity while adapting to various protocol requirements.

Inventive Principle:

Principle #35Parameter changes

4Productivity

If embedded devices are pushed to their performance limits to handle high bandwidth, then the data throughput increases, but the system becomes unreliable with deadlocks

Engineering Contradiction:

Improvedata throughputVSAvoidsystem stability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent extracts the protocol processing workload from the general-purpose CPU and OS, placing it in a dedicated hardware unit. This extraction allows the system to handle high bandwidth traffic without overloading the OS, preventing deadlocks while maintaining high throughput. The dedicated unit processes data at line rate without being affected by OS scheduling or resource constraints.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS7383425B2Massively reduced instruction set processor

Publication Date: 2008.06.03 PLEORA TECH

AI summary

This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video source without an operating system. The method relates to operation of a microprocessor which is suitably arranged to carry out the steps of the method. The method includes details of operation of the specialized microprocessor.