Multi-Stage Demodulator for Symbol Block Detection

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Solution Overview

Problem

Existing symbol block detection methods in DS-CDMA and non-spread systems face challenges with intersymbol interference (ISI) due to dispersive channels and MIMO transmission, leading to high computational complexity, especially in systems like HSPA and LTE, where maximum likelihood detection becomes impractical due to the large number of possible symbol combinations.

Innovation Solution

Incorporating a decoder into the Multi-Stage arbitration (MSA) process to produce modem bit likelihood values, which are used to construct candidate symbol values, reducing the number of combinations to be considered and thereby decreasing computational complexity through stages of detection assistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If maximum likelihood detection is used to detect symbol blocks, then detection accuracy is improved, but computational complexity becomes prohibitively large

Engineering Contradiction:
Improvedetection accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The detection process is divided into multiple stages: a first stage performs initial detection assistance to identify candidate symbol values, and a second stage performs final detection using reduced candidate combinations. This segmentation reduces computational complexity while maintaining detection accuracy by processing symbol blocks in manageable stages rather than evaluating all possibilities simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first stage of detection assistance performs preliminary identification of candidate symbol values before the final detection stage. By pre-filtering and identifying the most likely candidate symbol values in advance, the system reduces the search space for the second stage, thereby reducing overall computational complexity while preserving accuracy.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If the number of candidate symbol combinations is reduced, then computational complexity is decreased, but detection reliability may be compromised

Engineering Contradiction:
Improvecomputational complexityVSAvoiddetection reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The detection process uses feedback from the first stage to guide the second stage. The first stage identifies candidate symbol values and this information feeds back to constrain the second stage's search space. This feedback mechanism ensures that the reduced candidate combinations in the second stage are still reliable candidates, maintaining detection reliability while reducing complexity.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The first stage performs preliminary identification of the most likely candidate symbol values before the final detection. This preliminary action filters out unlikely combinations in advance, ensuring that the reduced set of candidates considered in the second stage maintains high reliability, thus balancing complexity reduction with accuracy preservation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8630372B2Method and apparatus for detecting a plurality of symbol blocks using a decoder
Publication Date: 2014.01.14 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US8630372B2 patent drawing
  • US8630372B2 patent drawing
  • US8630372B2 patent drawing

AI summary

Teachings presented herein offer a technique for using a demodulator to improve a demodulation process. For example, a demodulation unit according to an embodiment of the present invention may be a multi-stage demodulator and may include: a demodulator configured to receive a baseband signal and configured to produce modem bit likelihood values based on the received baseband signal; a decoder configured to receive and process the modem bit likelihood values to produce improved modem bit likelihood values; a candidate value generator configured to produce, based on the improved modem bit likelihood values, candidate symbol values for a group of one or more symbols; and a detector configured to receive the baseband signal and the candidate symbol values and configured to produce one of (a) final modem bit estimates and (b) candidate symbol values for a group of symbols.