MSB ADC Switching Scheme for Low-Voltage Reliable Conversion
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Solution Overview
Problem
Low power analog to digital converters face issues with parasitic diodes in comparators, leading to charge loss from sampling capacitors and unreliable conversions when input voltages exceed supply ranges, potentially damaging devices.
Innovation Solution
A most significant bits analog to digital converter system comprising a digital to analog converter, capacitive attenuator, and switching arrangement that inhibits the attenuator during sampling and enables it during conversion, ensuring consistent decision thresholds across main and MSB converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the comparator operates at low supply voltage to reduce power dissipation, then power efficiency is improved, but parasitic diodes can switch on when input voltages exceed supply ranges, causing charge loss from sampling capacitors and unreliable conversions
Solution Approach 1:
The analog-to-digital conversion is divided into two separate converters: a main ADC for the majority of bits and an MSB ADC for the most significant bits. This segmentation allows the MSB ADC to handle voltage excursions and protect the sampling capacitor, while the main ADC operates at low voltage for power efficiency. The switching arrangement further segments the operation by selectively enabling the MSB ADC only during conversion, not during sampling.
Solution Approach 2:
The MSB ADC acts as an intermediary protective layer between the sampling capacitor and the main ADC. It monitors and manages voltage excursions that could otherwise damage the sampling capacitor or cause charge loss through parasitic diodes, while allowing the main ADC to operate at low voltages for power efficiency.
2Use of energy by moving object
If a capacitive attenuator is used in the MSB ADC to scale down voltages, then the comparator can operate at lower voltages improving power efficiency, but the attenuator causes performance discrepancies between MSB and main ADC converters
Solution Approach 1:
The switching arrangement dynamically changes the operational parameters of the MSB ADC by selectively enabling or disabling the capacitive attenuator based on the operational phase. During sampling, the attenuator is disabled and the MSB ADC operates at full range. During conversion, the attenuator is enabled to scale down voltages for the comparator, allowing low-voltage operation while maintaining accuracy through phase-specific parameter adjustment.
3Use of energy by moving object
If the switching arrangement enables the attenuator during conversion, then power efficiency is improved through low-voltage comparator operation, but high-frequency components cause errors in the conversion process
Solution Approach 1:
The switching arrangement dynamically adjusts the attenuator's operation based on the conversion phase rather than maintaining a static configuration. This dynamic approach allows the system to optimize for power efficiency during conversion while managing high-frequency components through the controlled timing of attenuator engagement, reducing errors caused by high-frequency signals that would otherwise interfere with the conversion process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces errors caused by high-frequency components and allows the comparator to operate at lower supply voltages, enhancing power efficiency and accuracy while preventing voltage excursions that could damage the device.
Implementation Method 1
a capacitive attenuator for attenuating a signal received by the comparator
Implementation Method 2
a switching arrangement for inhibiting action of the attenuator during sampling and enabling the attenuator during conversion
Implementation Method 3
the voltage on the sampling capacitor is provided to one input of a comparator
Data Source
AI summary
A most significant bits analog to digital converter for determining a first P bits of an N bit analog to digital conversion, the most significant bits analog to digital converter comprising: a digital to analog converter a capacitive attenuator, and a switching arrangement for inhibiting action of the attenuator during sampling and enabling the attenuator during conversion.