MSB Error Correction via Adjacent Cell Comparison
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Solution Overview
Problem
As the number of data bits stored in flash memory cells increases, the narrowing of threshold voltage distributions leads to a higher probability of read errors due to coupling effects between adjacent cells, which burdens the error correction circuit with a growing number of erroneous data bits.
Innovation Solution
A flash memory system with a read circuit and control logic that successively reads data from selected and adjacent memory cells, using a compare circuit to correct data based on comparisons, thereby reducing the number of error bits corrected by the error correction circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of data bits stored in flash memory cells is increased, then the storage capacity is improved, but the threshold voltage distributions narrow and overlap, leading to increased read errors
Solution Approach 1:
The patent segments the error correction process into two distinct stages: a first error correction stage that processes data from selected memory cells, and a second error correction stage that processes data from adjacent memory cells. This segmentation allows the system to handle different types of errors systematically, addressing the reliability issue while maintaining high storage capacity.
Solution Approach 2:
The patent performs preliminary error correction on data from selected memory cells before processing data from adjacent memory cells. By applying error correction in a predetermined sequence, the system proactively reduces the number of erroneous bits that would otherwise burden the second error correction stage, thereby improving overall read reliability.
2Quantity of substance
If the number of data bits stored in flash memory cells is increased, then the storage capacity is improved, but the error correction circuit burden increases due to more erroneous data bits
Solution Approach 1:
The error correction circuit is divided into two functional segments: a first error correction circuit for selected memory cells and a second error correction circuit for adjacent memory cells. This segmentation distributes the computational burden across two specialized units, preventing any single circuit from becoming overwhelmed by the increased error rates associated with higher storage capacity.
Solution Approach 2:
The first error correction circuit performs preliminary correction on data from selected memory cells before the data is passed to the second error correction circuit. This preliminary action reduces the number of erroneous bits that reach the second circuit, thereby reducing its processing burden and overall system complexity.
3Manufacturing precision
If threshold voltage distributions are controlled precisely using ISPP scheme, then the manufacturing precision is improved, but the coupling effects between adjacent cells cause distribution widening and overlap
Solution Approach 1:
The patent introduces an intermediary error correction mechanism that operates between the memory cells and the data output. The error correction circuits act as mediators that detect and correct errors caused by coupling effects, allowing the system to maintain precise threshold voltage control while compensating for the reliability degradation caused by adjacent cell interference.
Solution Approach 2:
The patent changes the operational parameters of the error correction process by applying different correction strategies to selected versus adjacent memory cells. By adjusting the error correction approach based on cell position and error probability, the system maintains manufacturing precision while mitigating the effects of coupling-induced distribution widening.
Data Source
AI summary
A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.