MSM-Selector OTP Bit-Cell Layout for Low-Leakage Memory Arrays
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Solution Overview
Problem
Conventional OTP bit-cell designs for integrated circuits require significant die area and are prone to reliability issues due to the need for high-voltage MOS transistors, increasing design and manufacturing complexity.
Innovation Solution
Incorporating a selector with a Schottky junction or metal-semiconductor-metal (MSM) material stack in series with the OTP element, which acts as a transient voltage suppression (TVS) diode, reducing the need for access transistors and enabling smaller bit-cell size and higher reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MOS transistor-based access structures are used in OTP bit-cells, then the bit-cells can achieve sufficient transient current capabilities, but the die area increases significantly and reliability decreases due to source-drain short risks
Solution Approach 1:
The patent extracts the access transistor from the OTP bit-cell structure and replaces it with a selector device having diodic behavior. This removal of the MOS transistor eliminates the source-drain short risk while reducing the bit-cell area, as the selector device requires fewer components and occupies less space than a full transistor structure.
Solution Approach 2:
The patent changes the electrical parameters of the selector device to achieve diodic behavior with specific characteristics: a first threshold voltage for read operations and a higher second threshold voltage for programming operations. This parameter differentiation allows the selector to provide sufficient transient current during programming while maintaining low standby current, resolving the contradiction between reliability and area.
2Ease of manufacture
If high-voltage MOS transistors are used to enable OTP element programming, then the programming function is achieved, but the design and manufacturing complexity increases
Solution Approach 1:
The patent replaces the complex high-voltage MOS transistor with a simpler selector device that can be implemented using standard CMOS processes. The selector device uses a p-type transistor with specific dimensional ratios (width-to-length ratio) to achieve the desired diodic behavior, eliminating the need for specialized high-voltage transistor designs and simplifying the manufacturing process.
Solution Approach 2:
The patent achieves high-voltage programming capability through parameter optimization of a standard transistor rather than requiring specialized high-voltage devices. By adjusting the width-to-length ratio and applying specific voltage sequences (including negative voltages on the bit line), the selector device can safely program OTP elements without requiring complex high-voltage MOS transistor designs.
3Area of stationary object
If the selector provides sufficient transient current for OTP programming, then programming functionality is achieved, but the bit-cell area increases
Solution Approach 1:
The patent optimizes the selector device parameters to achieve dual-threshold behavior: a low first threshold voltage (0.3V-0.7V) for read operations and a higher second threshold voltage (1.8V-3.6V) for programming. This allows the selector to provide sufficient transient current during programming when needed while maintaining minimal area by using a compact transistor structure with optimized width-to-length ratio.
Solution Approach 2:
The patent implements dynamic voltage control where the selector device operates in different modes depending on the applied voltages. During read operations, the selector operates in a low-voltage mode with minimal current consumption. During programming, dynamic voltage sequences activate the selector to provide high transient current, achieving the required power capability without permanently requiring large device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a more compact and reliable OTP bit-cell architecture, reducing die area usage and minimizing the risk of source-drain shorts, while maintaining high transient current capabilities without catastrophic failure.
Implementation Method 1
Incorporating a selector with a Schottky junction or metal-semiconductor-metal (MSM) material stack in series with the OTP element, which acts as a transient voltage suppression (TVS) diode
Implementation Method 2
When the program voltage is dropped across terminals of antifuse 201, Joule heating and/or electromigration occurs within resistor 103 causing resistor 103 to physically degrade into an open circuit
Implementation Method 3
When the program voltage is dropped across terminals of antifuse 201, Joule heating and/or electromigration occurs within resistor 103 causing resistor 103 to physically degrade into an open circuit
Implementation Method 4
until voltage across the device exceeds a certain level, which then induces a permanent/irreversible low resistance/conductive path
Data Source
AI summary
One-time programmable (OTP) bit-cell for an integrated circuit (IC) that includes an OTP element, such as a fuse or antifuse, coupled in electrical series with a selector that comprises a Schottky junction. The selector may comprise a metal-semiconductor-metal (MSM) material stack operable as transient voltage suppression (TVS) device that experiences electrical breakdown at a voltage below a programming voltage of the OTP element. In response to a programming voltage, the MSM stack may breakdown and pass a transient current sufficient for programming the OTP element. In response to a lower (e.g., read) voltage, the MSM stack may breakdown and pass a transient current insufficient for programming, but sufficient to sense a state of the OTP element. In response to an even lower (e.g., half-read) voltage, the MSM stack may present a very high OTP bit-cell input impedance, reducing leakage and/or sneak path currents within an array of such bit-cells.