Multicore Shared Memory Controller Arbitration for Atomic Accesses
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Solution Overview
Problem
In multicore coherent systems, the interconnect becomes a bottleneck due to serial handling of diverse memory access requests from different components with varying cache structures and memory access types, leading to increased CPU stall overhead and reduced memory throughput.
Innovation Solution
The Multicore Shared Memory Controller (MSMC) unifies transaction sizes before arbitration, assigns two consecutive slots per cache line access to ensure atomicity, and eliminates bank synchronization by using back-to-back slots, allowing parallel access to multiple SRAM banks and optimizing memory access order for maximum bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interconnect handles memory access requests in a serial fashion to guarantee atomicity, then data coherence is maintained, but the interconnect becomes the access bottleneck and CPU stall overhead increases
Solution Approach 1:
The patent segments the memory access arbitration process by introducing separate arbitration mechanisms for different access types. Read requests and write requests are arbitrated independently through separate counters and slot assignment mechanisms, allowing parallel processing of different access types while maintaining atomicity through structured slot allocation.
Solution Approach 2:
The patent implements dynamic slot assignment where the arbiter assigns time slots dynamically based on access priority and type. Critical reads receive higher priority and are assigned slots accordingly, while non-critical accesses wait for available slots. This dynamic arbitration allows the system to adapt to varying workload conditions and maximize throughput while maintaining coherence.
2Loss of time
If cache components issue cache allocate accesses with critical line first request, then CPU stall overhead is reduced for that CPU, but other CPU's stall overhead may be extended and shared memory throughput reduced
Solution Approach 1:
The patent applies local quality by assigning different arbitration characteristics to different access types. Critical read requests receive prioritized treatment with dedicated slot assignment, while non-critical writes and reads follow standard arbitration. This localized optimization ensures that critical paths are minimized for individual CPUs without severely impacting overall system throughput.
Solution Approach 2:
The patent implements preliminary action through the look-ahead mechanism where the arbiter predicts future access patterns and pre-assigns slots accordingly. By anticipating critical reads and reserving slots in advance, the system reduces CPU stall overhead before it occurs, while managing overall throughput through coordinated slot allocation across all CPUs.
3Reliability
If the interconnect serially processes diverse memory access requests from components with varying cache structures, then data consistency is guaranteed, but access latency increases for all cores
Solution Approach 1:
The patent segments the arbitration process into separate counters for different access types (read, write, critical read). Each counter manages its own queue and slot assignment, allowing parallel processing of different access types. This segmentation enables the system to handle diverse access requests from components with varying cache structures without serializing all operations, thereby reducing latency while maintaining consistency.
Solution Approach 2:
The patent changes the arbitration parameters dynamically based on access type and priority. Critical reads are assigned higher priority weights and receive slot allocation accordingly, while non-critical accesses use standard timing. This parameter adjustment allows the system to optimize latency for critical paths without compromising the consistency guarantees required for all memory accesses.
Data Source
AI summary
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.