Multicore Shared Memory Controller Arbitration
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Solution Overview
Problem
In multicore coherent systems, the interconnect becomes a bottleneck due to serial handling of diverse memory access requests from components with different cache structures and access characteristics, leading to increased CPU stall overhead and reduced memory throughput.
Innovation Solution
The Multicore Shared Memory Controller (MSMC) unifies all transaction types before arbitration, prioritizes critical cache line access, and uses a return buffer to adjust data return order without performance loss, ensuring optimal bank access and bandwidth management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interconnect handles memory access requests in a serial fashion to guarantee atomicity, then data consistency is maintained, but memory throughput is reduced and CPU stall overhead increases
Solution Approach 1:
The patent segments memory access requests into different types (read, write, allocate, invalidate) and routes them through different arbitration paths. Read requests can be handled in parallel without affecting write atomicity, while write requests maintain serial handling for consistency. This segmentation allows concurrent processing of compatible request types, improving throughput while preserving data consistency for critical operations.
Solution Approach 2:
The arbitration mechanism dynamically adjusts the handling of different request types based on system state. Critical write requests that require atomicity are serialized, while non-critical read requests and compatible operations are allowed to proceed in parallel. The system dynamically prioritizes requests based on their consistency requirements, enabling flexible throughput optimization without compromising reliability.
2Adaptability or versatility
If the interconnect handles diverse memory access requests from components with different cache structures, then system compatibility is improved, but arbitration complexity increases
Solution Approach 1:
The patent implements a universal arbitration framework that handles multiple request types (read, write, allocate, invalidate) from various components with different cache structures through a unified interface. The arbitration logic is designed to be request-type-agnostic at the entry point, accepting diverse requests and routing them through appropriate handling paths, thereby supporting heterogeneous components without proportionally increasing arbitration complexity.
Solution Approach 2:
The patent introduces request classification and routing mechanisms as intermediary layers between the diverse components and the core arbitration logic. These intermediaries standardize incoming requests into a common format, extract relevant attributes, and route them to specialized handling paths. This mediation approach allows the system to support heterogeneous components with different cache structures while keeping the core arbitration logic relatively simple and modular.
3Speed
If critical line first requests are prioritized to reduce CPU cache miss stall overhead, then CPU performance is improved, but shared memory throughput is reduced due to extended stall overhead for other CPUs
Solution Approach 1:
The patent applies local quality by providing differentiated service to different request types and different CPU contexts. Critical line first requests from individual CPUs receive prioritized handling to minimize their stall overhead, while other requests maintain normal processing. This localized optimization ensures that each CPU's critical needs are met without uniformly degrading overall shared memory throughput, as only specific high-priority requests receive expedited service.
Solution Approach 2:
The patent dynamically changes arbitration parameters such as priority levels and service queues based on request type and system state. When a critical line first request is detected, the system adjusts arbitration parameters to favor that request temporarily, reducing its stall overhead. After service, parameters return to normal, allowing overall throughput to be maintained. This dynamic parameter adjustment enables selective performance optimization without sustained throughput degradation.
Data Source
AI summary
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. The two consecutive slots assigned per cache line access are always in the same direction for maximum access rate.