Metal-Silicon-Nitride Patterns for Semiconductor Integration
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Solution Overview
Problem
The challenge in semiconductor manufacturing is achieving higher levels of integration with fine patterns, which requires new exposure techniques and is difficult to achieve with existing methods.
Innovation Solution
The implementation of metal-silicon-nitride patterns in semiconductor devices, including a conductive line structure with a metal-silicon-nitride pattern providing both a contact and a diffusion barrier, allowing for precise layering and reduced thickness to enhance integration and operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional conductive line structures are used, then manufacturing is simpler, but integration level and operational speed are limited
Solution Approach 1:
The conductive line is divided into multiple distinct layers: a first conductive layer providing contact functionality and a second conductive layer providing diffusion barrier functionality. This segmentation allows each layer to be optimized for its specific function, enabling higher integration while maintaining manufacturability through standardized layering processes.
Solution Approach 2:
The patent employs composite material structures where different conductive materials are stacked together. The first conductive layer may use materials optimized for contact resistance, while the second conductive layer uses materials optimized for diffusion barrier properties. This composite approach enables simultaneous achievement of low contact resistance and effective diffusion prevention, critical for high-density integration.
2Speed
If thicker conductive lines are used, then manufacturing is easier, but parasitic capacitance increases reducing operational speed
Solution Approach 1:
Instead of reducing the thickness of a single conductive layer, the patent transitions to a multi-layer vertical structure. The total conductive path is distributed across multiple thin layers stacked vertically, maintaining low parasitic capacitance while allowing each layer to be formed using standard thin-film deposition techniques that are well-established in manufacturing.
Solution Approach 2:
The patent changes the electrical and physical parameters of the conductive structure by using different materials with optimized properties for each layer. The first conductive layer uses materials with low contact resistance, while the second layer uses materials with high diffusion barrier properties. This parameter optimization enables thin-layer construction that reduces capacitance while maintaining ease of manufacture through precise control of layer thickness and material composition.
3Quantity of substance
If finer patterns are used to achieve higher integration, then device density increases, but existing exposure techniques become insufficient
Solution Approach 1:
The conductive system is segmented into multiple layers that can be formed using separate exposure and patterning steps. This allows each layer to be optimized for its specific pitch and pattern requirements, enabling higher overall device density while using existing exposure techniques for each individual layer formation process.
Solution Approach 2:
The multi-layer conductive structure provides multiple functions: the first layer provides contact functionality and the second layer provides diffusion barrier functionality. This multi-functionality allows each layer to be patterned independently using standard exposure techniques, achieving high device density without requiring new exposure methodologies for the entire conductive system.
4Reliability
If contact and diffusion barrier functions are combined in one layer, then structure is simpler, but functional performance is compromised
Solution Approach 1:
The conductive line is segmented into functionally distinct layers: the first conductive layer is optimized for contact functionality with materials and thicknesses selected to minimize contact resistance, while the second conductive layer is optimized for diffusion barrier functionality with materials selected to prevent dopant diffusion. This functional segmentation ensures reliable performance of both contact and diffusion barrier operations simultaneously.
Solution Approach 2:
Each conductive layer is designed with local quality optimized for its specific function. The first conductive layer has material composition and thickness optimized for electrical contact, while the second conductive layer has material composition and thickness optimized for diffusion prevention. This localized optimization of material properties at each layer ensures that both contact and diffusion barrier functions perform reliably without compromising overall structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the formation of semiconductor memory devices with improved integration and reduced parasitic capacitance, enhancing the operational speed and efficiency of semiconductor devices.
Implementation Method 1
configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern
Implementation Method 2
configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern, where the contact can include an ohmic contact
Data Source
AI summary
A semiconductor memory device can include a first conductive line crossing over a field isolation region and crossing over an active region of the device, where the first conductive line can include a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and can be configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern.