MTJ Antifuse Trim-Enable Logic for Defect-Tolerant Reads
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Solution Overview
Problem
Manufacturing defects in magnetoresistive memory devices, such as MRAM, lead to electrical shorts or partial shorts in antifuse magnetic tunnel junctions (MTJs), causing erroneous readings and reducing chip yield and performance.
Innovation Solution
Implementing trim-enable MTJs associated with antifuse MTJs, where a trim-enable bit determines the reading strategy for antifuse bits, allowing some defects to be ignored, and using scan-chain circuitry to selectively read or assume states based on the trim-enable bit's state, combined with error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manufacturing precision is improved to eliminate all defects, then reliability is improved, but manufacturing cost and complexity increase significantly
Solution Approach 1:
The patent applies preliminary action by programming trim-enable bits before antifuse bits during configuration. This preliminary programming of trim-enable bits establishes a reading strategy that will be used later to interpret antifuse bit states, allowing the system to pre-compensate for potential manufacturing defects before they affect functionality.
Solution Approach 2:
The patent converts the harmful effect of manufacturing defects into a beneficial feature by using trim-enable bits to selectively ignore defective antifuse bits. Instead of requiring zero defects, the system embraces the possibility of defects and uses the trim-enable mechanism to identify and bypass problematic bits, thereby converting a manufacturing weakness into a tolerable or even advantageous characteristic.
2Measurement precision
If all antifuse bits are read to ensure accuracy, then measurement precision is improved, but energy consumption increases
Solution Approach 1:
The patent applies partial action by selectively reading only those antifuse bits that are necessary based on the trim-enable bit states. Instead of reading all antifuse bits uniformly, the system performs partial reads based on the configuration established by trim-enable bits, thereby reducing unnecessary energy expenditure while maintaining sufficient measurement precision for functional operation.
3Productivity
If defect tolerance is increased to allow higher defect rates, then productivity is improved, but measurement precision deteriorates
Solution Approach 1:
The patent introduces trim-enable bits as an intermediary layer between the physical antifuse bits and the logical interpretation of their states. These intermediary bits provide a configuration mechanism that allows the system to tolerate manufacturing defects in antifuse bits while maintaining accurate logical state determination through selective reading and interpretation based on trim-enable bit values.
4Reliability
If trim-enable bits are programmed to ignore defects, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of defect detection and defect tolerance into a single integrated mechanism using trim-enable bits. Instead of requiring separate error detection circuits, correction algorithms, and tolerance mechanisms, the system combines these functions into the bit configuration and reading process itself, where trim-enable bits serve multiple purposes in establishing both the reading strategy and the tolerance to defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances chip yield and performance by reducing the impact of manufacturing defects, allowing higher defect rates without affecting functionality, and improving energy efficiency.
Implementation Method 1
A magnetoresistive stack used in a memory device (e.g., MRAM) includes at least one non-magnetic layer (for example, at least one dielectric layer or a non-magnetic yet electrically conductive layer) disposed between a 'fixed' magnetic region and a 'free' magnetic region, each including one or more layers of ferromagnetic materials.
Data Source
AI summary
A device may include a set of antifuse magnetic tunnel junctions (MTJs). A device may include a trim-enable MTJ associated with the set of antifuse MTJs, wherein each of the set of antifuse MTJs and the trim-enable MTJ has a logical state, the logical state being a first logical state or a second logical state. A device may include a circuit configured to determine the logical state of each of the set of antifuse MTJs and the trim-enable MTJ, wherein the logical state of each antifuse MTJ in the set of antifuse MTJs is read when the trim-enable MTJ has the second logical state, and wherein the logical state of every antifuse MTJ in the set of antifuse MTJs is determined to be the first logical state when the trim-enable MTJ has the first logical state.