MTJ Antifuse Trim-Enable Logic for Defect-Tolerant Reads
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Solution Overview
Problem
Manufacturing defects in magnetoresistive memory devices, such as MRAM, cause electrical shorts or partial shorts in antifuse magnetic tunnel junctions (MTJs), leading to erroneous readings and reduced chip yield and performance.
Innovation Solution
Implementing trim-enable MTJs associated with antifuse MTJs, where trim-enable bits determine the reading strategy for antifuse bits, allowing some defects to be ignored, and using scan-chain circuitry to selectively read or assume states based on trim-enable bit logic, combined with error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trim-enable MTJs are implemented to selectively read or ignore antifuse MTJ states, then chip yield and performance are improved by tolerating manufacturing defects, but device complexity increases due to additional circuitry and control logic
Solution Approach 1:
The antifuse block is divided into multiple groups, each associated with a trim-enable bit. This segmentation allows selective processing of different regions based on their defect status, improving yield without requiring complete reprocessing of the entire block.
Solution Approach 2:
Trim-enable bits are introduced as intermediary elements between the read circuitry and the antifuse MTJs. These intermediary bits control whether to read actual antifuse states or use default values, acting as a buffer that simplifies the overall control logic while enabling defect tolerance.
2Measurement precision
If all antifuse MTJ states are read individually to ensure accurate configuration data, then measurement precision is improved, but loss of time increases due to extended read operations
Solution Approach 1:
Instead of reading all antifuse MTJ states, the system performs partial reads only for groups where trim-enable bits indicate potential defects. For groups with clean trim-enable bits, default values are used without reading, significantly reducing read time while maintaining configuration accuracy.
Solution Approach 2:
The trim-enable bits are processed beforehand to identify which antifuse groups require reading. This preliminary action allows the system to skip reading operations for clean groups, optimizing the read sequence and reducing overall read time while ensuring accurate reading only where necessary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances chip yield and performance by reducing the impact of manufacturing defects, allowing higher defect rates without affecting functionality, and improving energy efficiency.
Implementation Method 1
switching, programming, and/or controlling the direction of magnetization vectors in the magnetic layer(s) of the free magnetic region
Implementation Method 2
A magnetoresistive stack used in a memory device (e.g., MRAM) includes at least one non-magnetic layer disposed between a 'fixed' magnetic region and a 'free' magnetic region
Data Source
Figure 1~2
Figure 3
Figure 4A~4B
AI summary
A device may include a set of antifuse magnetic tunnel junctions (MTJs). A device may include a trim-enable MTJ associated with the set of antifuse MTJs, wherein each of the set of antifuse MTJs and the trim-enable MTJ has a logical state, the logical state being a first logical state or a second logical state. A device may include a circuit configured to determine the logical state of each of the set of antifuse MTJs and the trim-enable MTJ, wherein the logical state of each antifuse MTJ in the set of antifuse MTJs is read when the trim-enable MTJ has the second logical state, and wherein the logical state of every antifuse MTJ in the set of antifuse MTJs is determined to be the first logical state when the trim-enable MTJ has the first logical state.