Integrated Memory Capacitor Fabrication via MTJ Height
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Solution Overview
Problem
Conventional metal on metal (MOM) and poly on poly (POP) capacitors in integrated circuits require numerous processing steps, increasing manufacturing costs due to additional mask steps, which is undesirable in the competitive integrated circuit fabrication industry.
Innovation Solution
The method involves forming a magnetic tunnel junction (MTJ) structure and a capacitor over a semiconductor substrate, where the capacitor's electrodes are separated by the height of the MTJ structure, allowing for the integration of capacitors and memory structures using fewer processing steps by utilizing conductive vias and dielectric layers to increase capacitance and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional MOM or POP capacitors are formed using traditional processing methods, then precise capacitance values and high capacitance per unit area are achieved, but the number of processing steps increases and manufacturing cost increases
Solution Approach 1:
The patent merges the capacitor formation process with the existing memory structure fabrication process. The capacitor electrodes are formed using the same conductive layers and processing steps that create the memory interconnect structures, eliminating the need for separate capacitor-specific processing steps while maintaining precise capacitance values
Solution Approach 2:
The conductive layers and processing steps are designed to serve dual purposes: forming both memory interconnect structures and capacitor electrodes. The same deposition and patterning processes that create memory structures also define the capacitor geometry, making the manufacturing process universal for both functions
2Manufacturing precision
If additional mask steps are added to form precise capacitor structures, then capacitance precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines capacitor patterning with memory structure patterning operations. The mask steps required for defining capacitor electrodes are integrated into the existing mask sequence used for memory interconnect formation, so no additional mask steps are required beyond what is already needed for memory fabrication
Solution Approach 2:
The patterning process is designed to simultaneously define both memory structures and capacitor electrodes using the same masks and etching conditions, making the manufacturing process universal and eliminating cost penalties associated with additional specialized patterning steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in integrated circuits with improved capacitance values per unit area and reduced manufacturing costs by integrating capacitors and memory structures with fewer processing steps, enhancing efficiency and cost-effectiveness.
Implementation Method 1
forming a magnetic tunnel junction (MTJ) structure over the substrate in the memory region. The MTJ structure includes a lowest surface formed by a bottom electrode and an uppermost surface formed by a top electrode
Implementation Method 2
forming a capacitor over the substrate in the memory region. The capacitor includes a lower capacitor electrode element and an upper capacitor electrode element, and the upper capacitor electrode element is separated from the lower capacitor electrode element by a distance equal to the height of the MTJ structure
Data Source
AI summary
Integrated circuits with integrated memory devices and high capacitors, and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming, from a lower conductive layer, a lower memory interconnect and a lower capacitor interconnects over a substrate. The method further includes forming a conductive memory via coupled to the lower memory interconnect and a conductive capacitor vias coupled to the lower capacitor interconnect. Also, the method includes forming a memory structure over the memory via and forming a capacitor dielectric layer over the memory structure and over the capacitor via. Further, the method includes forming, from an upper conductive layer, an upper memory interconnect coupled to the memory structure and an upper capacitor interconnects over the capacitor dielectric layer over the capacitor via. The capacitor via, capacitor dielectric layer, and upper capacitor interconnects form the high capacitor.