Fast BER Testing of MTJ Cells via Signal Reflections
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Solution Overview
Problem
Current methods for testing bit-error rate (BER) in Spin Torque Transfer Magnetic Random Access Memory (STT-MRAM) cells are too slow and costly, requiring impractical times to achieve statistical significance for commercialization, especially at the wafer level, due to the need for CMOS logic and slow read operations.
Innovation Solution
A method and apparatus for fast BER measurement using direct electrical connections to memory cells on wafers or chips, allowing unbuffered, high-rate switching between resistance states without CMOS logic, utilizing signal reflections to detect switching events, enabling switching rates of over 10^7 per second with standard laboratory equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional BER measurement methods using pulsed write operations followed by slow read operations are used, then measurement accuracy can be achieved, but testing speed becomes too slow (3 attempts per second) to enable large amounts of switching events for statistical significance
Solution Approach 1:
The patent replaces the mechanical/electrical read operation (resistance sensing) with an optical detection method. By coupling a laser to the MTJ cell and detecting reflected light intensity, the system achieves fast readout without the speed limitations of electrical read operations. The laser reflection method enables switching rates exceeding 10^7 per second while maintaining BER measurement accuracy, directly resolving the contradiction between measurement precision and productivity.
2Ease of operation
If CMOS control structures and selection transistors are used to control current flow through MTJ cells, then proper cell selection and control can be achieved, but device complexity and testing cost increase significantly
Solution Approach 1:
The patent extracts and removes the CMOS control structures and selection transistors from the testing system. By using direct electrical connections to wafer contact pads and optical detection, the method eliminates the need for complex CMOS circuitry that would normally be required to control and read MTJ cells. This reduction in device complexity enables wafer-level testing without the overhead of embedded CMOS logic, directly addressing the contradiction between ease of operation and device complexity.
3Reliability
If MTJ cells are embedded in STT-MRAM CMOS circuitry and packaged for testing, then proper testing environment can be provided, but testing cost and time requirements become impractical for wafer-level screening
Solution Approach 1:
The patent performs preliminary actions by establishing direct electrical connections to the MTJ cells on the wafer surface before any testing begins. By using probe contacts to connect to wafer contact pads and implementing optical detection, the system prepares the testing environment in advance without requiring time-consuming packaging or embedding in CMOS circuitry. This preliminary setup enables immediate wafer-level BER testing, significantly reducing the loss of time while maintaining reliable testing conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces BER test time by multiple decades, allowing for rapid estimation of MTJ cell designs and reducing development time and costs by enabling fast, high-speed BER testing at the wafer level.
Implementation Method 1
The resistivity of the whole MTJ layer stack changes when the magnetization of the free layer changes direction relative to that of the reference layer, exhibiting a low resistance state when the magnetization orientations of the two ferromagnetic layers are substantially parallel and a high resistance when they are anti-parallel
Implementation Method 2
The test setup configures the impedance of the transmission line to be mismatched to the impedance of the memory cell so that signal reflections from the memory cell on the transmission line are a function of the resistance state of the memory cell
Implementation Method 3
Writing the cells requires a sufficiently high DC current flowing through the MTJ stack between the top and bottom metal contacts to induce a spin transfer torque that orients (switches) the free layer into the desired direction
Data Source
AI summary
A testing method is described for performing a fast bit-error rate (BER) measurement on resistance-based RAM cells, such MTJ cells, at the wafer or chip level. Embodiments use one or more specially designed test memory cells fabricated with direct electrical connections between the two electrodes of the cell and external contact pads (or points) on the surface of the wafer (or chip). In the test setup the memory cell is connected an impedance mismatched transmission line through a probe for un-buffered, fast switching of the cell between the high and low resistance states without the need for CMOS logic to select and drive the cell. The unbalanced transmission line is used generate signal reflections from the cell that are a function of the resistance state. The reflected signal is used to detect whether the test cell has switched as expected.