Fe-Free MTJ Device Using Damascene Process and Passivation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional magnetic tunnel junction (MTJ) device manufacturing is hindered by the incompatibility of iron (Fe) with CMOS processes, leading to increased costs and device size due to the need for dedicated equipment and potential damage to the tunnel dielectric layer during etching, resulting in low yield rates and magnetic flux leakage.
Innovation Solution
The use of CMOS-compatible ferromagnetic materials free of Fe, combined with a damascene process to form a cup-shaped MTJ structure, and a passivation layer to seal the sidewalls and prevent magnetic flux leakage, allowing for integration with existing CMOS manufacturing lines and reducing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Fe component is added to ferromagnetic materials to enhance magnetism, then magnetic properties are improved, but compatibility with CMOS processes deteriorates requiring additional dedicated equipment
Solution Approach 1:
The patent changes the material composition parameters by removing Fe component from the ferromagnetic layer, transitioning from Fe-containing materials (CoFeB, CoFe) to Fe-free materials (Co, CoB, CoW, CoMo). This parameter change maintains adequate magnetism while achieving CMOS process compatibility and eliminating the need for dedicated equipment
Solution Approach 2:
The patent employs composite material strategies by combining Co with other elements (B, W, Mo) to create alternative ferromagnetic materials that do not require Fe. These composite materials achieve the necessary magnetic properties through different compositional ratios and layer structures, enabling integration with CMOS processes
2Ease of manufacture
If conventional etching methods are used to pattern MTJ, then cost is reduced and pattern is minimized, but damage to tunnel dielectric layer occurs resulting in low yield rates
Solution Approach 1:
The patent applies preliminary protective actions by forming a capping layer (such as TaN or TiN) over the tunnel dielectric layer before etching. This capping layer protects the tunnel dielectric from damage during subsequent etching processes, preventing yield loss while allowing the use of cost-effective etching methods
Solution Approach 2:
The patent introduces a protective capping layer structure that acts as a cushion between the etching process and the tunnel dielectric layer. This beforehand cushioning prevents direct contact between the etchant and the sensitive tunnel dielectric, eliminating damage while maintaining manufacturing efficiency
3Reliability
If tri-layered SAF structure is used to prevent magnetic flux leakage, then flux leakage is reduced, but device size increases which is disadvantageous for reduced dimensions
Solution Approach 1:
The patent extracts and removes the tri-layered SAF structure from the MTJ device, replacing it with a simpler single-layer or dual-layer ferromagnetic structure. By taking out the unnecessary SAF layers, the device achieves adequate flux containment through alternative means (such as optimized magnetization directions and interface effects) while significantly reducing device size for scaled dimensions
4Reliability
If dedicated equipment is introduced for Fe-contained MTJ manufacturing, then magnetism enhancement is achieved, but manufacturing cost increases
Solution Approach 1:
The patent achieves universality by designing an MTJ structure that can be manufactured using standard CMOS process equipment. By removing Fe component and using Fe-free ferromagnetic materials, the same deposition and etching tools used for CMOS transistors can also fabricate the MTJ device, eliminating the need for dedicated equipment and reducing manufacturing costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, minimizes device size, and enhances signal quality and fault-tolerance by eliminating the need for additional equipment and preventing magnetic flux leakage, while maintaining compatibility with CMOS processes.
Implementation Method 1
tunnel dielectric layer 1043
Implementation Method 2
electron spin polarization effect
Implementation Method 3
anti-ferromagnetic pinning layer 1045
Data Source
AI summary
Using a damascene process, a cup-shaped MTJ device is formed in an opening within a dielectric layer. A passivation layer is formed on the top surfaces of the sidewalls of the cup-shaped MTJ device to enclose the top of the sidewalls, thereby reducing magnetic flux leakage. Accordingly, the MTJ device may be fabricated using the same equipment that are compatible with and commonly used in CMOS technologies/processes.