MTJ Electrode Segmentation for MRAM Area Reduction
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Solution Overview
Problem
Current magnetic field sensor technologies, such as MRAM devices, face issues of high chip area, high cost, high power consumption, limited sensitivity, and susceptibility to temperature variations.
Innovation Solution
A semiconductor memory device is developed using a magnetic tunneling junction (MTJ) stack layer with a specific manufacturing method involving multiple interlayer dielectric layers, etch stop layers, and electrode formations to optimize the device's design and reduce material consumption, including the use of ultra-low dielectric constant materials and etch stop layers like nitride-doped silicon carbide, and the formation of step heights between memory and logic regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If magnetic field sensor technologies (MRAM devices) are used, then data storage capability is achieved, but chip area increases
Solution Approach 1:
The patent divides the upper electrode layer into two distinct regions: a first upper electrode layer over the memory region and a second upper electrode layer over the logic circuit region. This segmentation allows each region to have optimized electrode thickness, reducing overall chip area while maintaining data storage functionality in the memory region.
Solution Approach 2:
The patent applies different electrode thicknesses to different regions: the first upper electrode layer in the memory region has sufficient thickness for data storage, while the second upper electrode layer in the logic circuit region has reduced thickness. This local quality differentiation optimizes chip area without compromising memory functionality.
2Reliability
If magnetic field sensor technologies (MRAM devices) are used, then data storage is achieved, but power consumption increases
Solution Approach 1:
The patent implements local quality by providing full-thickness upper electrode only in the memory region where data storage is required, while reducing electrode thickness in the logic circuit region. This localized optimization reduces overall power consumption while maintaining data storage capability.
3Ease of manufacture
If uniform upper electrode layer is formed over entire substrate, then manufacturing simplicity is maintained, but material consumption increases
Solution Approach 1:
The patent uses a patterned mask layer with first and second regions having different thicknesses to achieve local quality differentiation. The first region corresponds to the memory region and the second region corresponds to the logic circuit region, allowing selective material deposition that reduces overall material consumption while maintaining manufacturing feasibility.
4Reliability
If thicker upper electrode layer is used, then device reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the upper electrode layer into two parts with different thicknesses using a patterned mask. This segmentation allows the memory region to have thicker electrodes for reliability while the logic region has thinner electrodes, managing manufacturing complexity through structured differentiation.
Solution Approach 2:
The patent forms the patterned mask layer with varying thickness before depositing the upper electrode layer. This preliminary action pre-establishes the thickness profile, simplifying the subsequent electrode formation process and managing manufacturing complexity through advance preparation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a more efficient, cost-effective, and sensitive semiconductor memory device with reduced power consumption and improved temperature stability, addressing the shortcomings of existing technologies.
Implementation Method 1
Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices
Data Source
AI summary
A method of forming a semiconductor memory device is disclosed. A top electrode layer is formed on the MTJ stack layer. A patterned buffer layer is formed to cover only the logic circuit region. A hard mask layer is formed on the top electrode layer and the patterned buffer layer. A patterned resist layer is formed on the hard mask layer. A first etching process is performed to etch the hard mask layer and the top electrode layer not covered by the patterned resist layer in the memory region and the hard mask layer, the patterned buffer layer and the top electrode layer in the logic circuit region, thereby forming a top electrode on the MTJ stack layer in the memory region and a remaining top electrode layer covering only the logic circuit region on the MTJ stack layer.